_start.s

QNX ADS BSP code for i.MX27 chips

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */


/*
 * Reset code for Freescale MX21ADS board
 */

#include <arm/mx21.h>

#define	MMU_I	0x1000

	.text
	.align	2
	.globl	_start

_start:
	mov     r0, #0
	mcr     15, 0, r0, cr7, cr7, 0
	mcr     15, 0, r0, cr8, cr7, 0
	mcr     15, 0, r0, cr7, cr10, 4

	mov		r0, #MX21_AIPI1_BASE
	mov		r1, #0x00000304
	str     r1, [r0, #MX21_AIPI_PSR0]
	mvn     r2, r1
	str     r2, [r0, #MX21_AIPI_PSR1]
	add		r0, r0, #0x00020000
	mov		r1, #0x3F000000
	orr		r1, r1, #0x00FC0000
	str     r1, [r0, #MX21_AIPI_PSR0]
	mvn     r2, #0
	str     r2, [r0, #MX21_AIPI_PSR1]

	ldr     r0, =MX21_SYSCTL_BASE
	mov     r1, #3
	str     r1, [r0, #0x50]
	mvn     r1, #0x36
	str     r1, [r0, #0x14]

	ldr     r0, =MX21_MAX_BASE
	add		r1, r0, #0x100
	add		r2, r1, #0x100
	add		r3, r2, #0x100
	add		r4, r3, #0x100
	add		r5, r4, #0x100
	ldr		r6, =0x00123045
	str     r6, [r0]
	str     r6, [r0, #4]
	str     r6, [r1]
	str     r6, [r1, #4]
	str     r6, [r2]
	str     r6, [r2, #4]
	str     r6, [r3]
	str     r6, [r3, #4]
	mov     r6, #1
	str     r6, [r0, #0x14]
	str     r6, [r1, #0x14]
	mov     r7, #4
	str     r7, [r2, #0x14]
	mov     r8, #5
	str     r8, [r3, #0x14]
	str     r6, [r0, #0x10]
	str     r6, [r1, #0x10]
	str     r7, [r2, #0x10]
	str     r8, [r3, #0x10]
	mov     r6, #0
	str     r6, [r0, #0x800]
	str     r6, [r1, #0x800]
	str     r6, [r2, #0x800]
	str     r6, [r3, #0x800]
	str     r6, [r4, #0x800]
	str     r6, [r5, #0x800]

	/*
	 * Explicitly set MPLL 266MHz
	 */
	ldr     r0, =MX21_CRM_BASE
	ldr     r1, =0x007B1C73
	str     r1, [r0, #MX21_CRM_MPCTL0]
	mov     r1, #0x40
	str     r1, [r0, #MX21_CRM_MPCTL1]
	ldr     r1, =0x03B02227
	str     r1, [r0, #MX21_CRM_SPCTL0]
	ldr     r1, [r0, #MX21_CRM_CSCR]
	orr     r1, r1, #0x00600000
	str     r1, [r0, #MX21_CRM_CSCR]
0:
	ldr     r1, [r0, #MX21_CRM_SPCTL1]
	ands    r1, r1, #0x8000
	beq     0b
0:
	ldr     r1, [r0, #MX21_CRM_MPCTL1]
	ands    r1, r1, #0x8000
	beq     0b

	ldr     r1, [r0, #MX21_CRM_CSCR]
	and     r1, r1, #0xE0000000
	ldr     r2, =0x17000607
	orr     r1, r1, r2
	str     r1, [r0, #MX21_CRM_CSCR]
	bic     r1, r1, #0xE0000000
	str     r1, [r0, #MX21_CRM_CSCR]
	ldr     r1, =0x64197007
	str     r1, [r0, #MX21_CRM_PCDR0]
	ldr     r1, =0x02070705
	str     r1, [r0, #MX21_CRM_PCDR1]
	ldr     r1, =0x3108480F
	str     r1, [r0, #MX21_CRM_PCCR0]
	mov     r1, #0x6000000
	str     r1, [r0, #MX21_CRM_PCCR1]

	/*
	 * Small delay
	 */
	mov		r3, #0x1000
0:
	subs	r3, r3, #1
	bne     0b

	/*
	 * Configure SDRAM Controller
	 */

	/* Set Precharge Command */
	mov     r1, #MX21_SDRAMC_BASE
	ldr     r4, =0x02120300
	orr		r2, r4, #0x90000000
	str     r2, [r1]

	/* Issue Precharge all Command */
	ldr     r3, =0xC0200000
	ldr     r2, [r3]

	/* Set AutoRefresh Command */
	orr		r2, r4, #0xA0000000
	str     r2, [r1]

	/* Issue AutoRefresh Command */
	mov		r3, #0xC0000000
	ldr     r2, [r3]
	ldr     r2, [r3]
	ldr     r2, [r3]
	ldr     r2, [r3]
	ldr     r2, [r3]
	ldr     r2, [r3]
	ldr     r2, [r3]
	ldr     r2, [r3]

	/* Set Mode Register */
	orr		r2, r4, #0xB0000000
	str     r2, [r1]

	/* 
	 * Issue Mode Register Command
	 * Burst Length = 8
	 */
	ldr     r3, =0xC0119800
	ldr     r2, [r3]

	/* 
	 * Set to Normal Mode
	 *  From the spec of the SDRAM K4S56163LC-RG75000,
	 * 1. tRCD = 19ns minimum  -> RCD = 3 clk (SDCLK=133MHz) -> SRCD = 11b
	 * 2. tRP  = 19ns minimum  -> RP  = 3 clk (SDCLK=133MHz) -> SRP  = 0b
	 * 3. tRC  = 65ns minimum  -> RC  = 9 clk (SDCLK=133MHz) -> SRC  = 1001b
	 * 4. refresh rate = 8192rows/64ms -> SREFR = 11b
	 */
	ldr     r2, =0x8212C304
	str     r2, [r1]

	/*
	 * Configure External Interface
	 */
	ldr     r1, =MX21_EIM_BASE
	ldr     r2, =0x00000801
	str     r2, [r1, #MX21_EIM_CS0U]
	orr		r2, r2, #0x00000E00
	str     r2, [r1, #MX21_EIM_CS0L]
	mov     r2, #0x2000
	str     r2, [r1, #MX21_EIM_CS1U]
	ldr     r2, =0x11118501
	str     r2, [r1, #MX21_EIM_CS1L]
	ldr     r1, =0x10027000
	ldr     r2, [r0, #MX21_EIM_CS3U]
	bic     r2, r2, #0xF000
	orr     r2, r2, #0x7000
	str     r2, [r1, #MX21_EIM_CS3U]
	ldr		r2, =0x02070705
	str		r2, [r1, #MX21_EIM_CS3L]

	/*
	 * Enable I cache for speed
	 */
	mov		r0, #MMU_I
	mcr		p15, 0, r0, c1, c0, 0
	mov		r0, r0
	mov		r0, r0
	mov		r0, r0
	mov		r0, r0

	/*
	 * Set stack pointer
	 */
	mov		r0, #0xC0000000
	add		sp, r0, #0xF000		/* Stack top = 0xC000F000 */

	bl		main

	/*
	 * In case return from main
	 */
	b		_start