crys8900.h

QNX ADS BSP code for i.MX27 chips

#define CS8900_TXCOL			0x0132	/* Transmit Collision Count */

#define CS8900_LINEST			0x0134	/* Line State Register */

#define CS8900_SELFST			0x0136	/* Self State register */
	#define SELFST_ACTIVE_33V		0x0040
	#define SELFST_INIT_DONE		0x0080
	#define SELFST_SI_BUSY			0x0100
	#define SELFST_EEPROM_PRESENT	0x0200
	#define SELFST_EEPROM_OK		0x0400
	#define SELFST_EL_PRESENT		0x0800
	#define SELFST_EE_SIZE_64		0x1000

#define CS8900_BUSST			0x0138	/* Bus Status */
	#define	BUSSTAT_RDY4TXNOW	0x0100
	#define BUSSTAT_TXBIDERR	0x0080

#define CS8900_TDR				0x013C	/* Time Domain Reflectometry */

#define CS8900_AUTONEGST		0x013E	/* Auto Neg Status */
	#define AUTONEGST_BUSY			0x0080
	#define AUTONEGST_FLP_LINK		0x0100
	#define AUTONEGST_FLP_LINK_GOOD	0x0800
	#define AUTONEGST_LINK_FAULT	0x1000
	#define AUTONEGST_HDX_ACTIVE	0x4000
	#define AUTONEGST_FDX_ACTIVE	0x8000

#define CS8900_TXCMD			0x0144	/* Tx Command */

#define CS8900_TXLEN			0x0146	/* Tx Length */

#define CS8900_LAF				0x0150	/* Hash Table */

#define CS8900_IA				0x0158	/* Physical Address Register */

#define CS8900_RX_STAT			0x0400	/* Receive start of frame */

#define CS8900_RX_LEN			0x0402	/* Receive Length of frame */

#define CS8900_RX_FRAME			0x0400	/* Receive frame pointer */

#define CS8900_TX_FRAME			0x0A00	/* Transmit frame pointer */


/* Receive Header data of each packet */
#define RBUF_EVENT_LOW			0   	/* Low byte of RxEvent - status of received frame */
#define RBUF_EVENT_HIGH			1   	/* High byte of RxEvent - status of received frame */
#define RBUF_LEN_LOW			2   	/* Length of received data - low byte */
#define RBUF_LEN_HI				3   	/* Length of received data - high byte */
#define RBUF_HEAD_LEN			4   	/* Length of this header */

/* EEPROM Commands */
#define ERSE_WR_ENBL			0x00F0
#define ERSE_WR_DISABLE			0x0000

#define EEPROM_WRITE_EN			0x00F0
#define EEPROM_WRITE_DIS		0x0000
#define EEPROM_WRITE_CMD		0x0100
#define EEPROM_READ_CMD			0x0200

/* Byte offsets into the EEPROM configuration buffer */
#define ISA_CNF_OFFSET			0x6
#define TX_CTL_OFFSET			(ISA_CNF_OFFSET + 8)	/* 8900 eeprom */
#define AUTO_NEG_CNF_OFFSET		(ISA_CNF_OFFSET + 8)	/* 8920 eeprom */

#define N_CNF_FORCE_FDX			0x8000
#define N_CNF_NLP_ENABLE		0x0200
#define N_CNF_NEG_ENABLE		0x0100
#define N_CNF_ALLOW_FDX			0x0080
#define N_CNF_IMM				0x0040				/* ignore missing media */
#define N_CNF_MASK				( N_CNF_FORCE_FDX | N_CNF_NLP_ENABLE | N_CNF_NEG_ENABLE | N_CNF_ALLOW_FDX )


#define ADAPTER_CNF_OFFSET		(AUTO_NEG_CNF_OFFSET + 2)
	#define A_CNF_10B_T				0x0001
	#define A_CNF_AUI				0x0002
	#define A_CNF_10B_2				0x0004
	#define A_CNF_MEDIA_TYPE		0x0060
	#define A_CNF_MEDIA_AUTO		0x0000
	#define A_CNF_MEDIA_10B_T		0x0020
	#define A_CNF_MEDIA_AUI			0x0040
	#define A_CNF_MEDIA_10B_2		0x0060
	#define A_CNF_DC_DC_POLARITY	0x0080
	#define A_CNF_NO_AUTO_POLARITY	0x2000
	#define A_CNF_LOW_RX_SQUELCH	0x4000
	#define A_CNF_EXTND_10B_2		0x8000

#define PACKET_PAGE_OFFSET		0x8

/* Bit definitions for the ISA configuration word from the EEPROM */
#define I_CNF_INT_NO_MASK			0x000F
#define I_CNF_DMA_NO_MASK			0x0070
#define I_CNF_ISA_DMA_64K			0x0200
#define I_CNF_ISA_AUTO_RXDMA		0x0400
#define I_CNF_ISA_RXDMA				0x0800
#define I_CNF_DMA_BURST				0x1000
#define I_CNF_STREAM_TRANSFER		0x2000
/*define I_CNF_SHARED				0x4000 */
#define I_CNF_ANY_ISA_DMA			( I_CNF_ISA_AUTO_RXDMA | I_CNF_ISA_RXDMA )

#define CS8900					0x0000
#define CS8920					0x4000   
#define CS8920M					0x6000   
#define REVISION_BITS			0x1F00
#define EEVER_NUMBER			0x12
#define CHKSUM_LEN				0x14
#define CHKSUM_VAL				0x0000
#define START_EEPROM_DATA		0x001c		/* Offset into eeprom for start of data */
#define IRQ_MAP_EEPROM_DATA		0x0046		/* Offset into eeprom for the IRQ map */
#define IRQ_MAP_LEN				0x0004		/* No of bytes to read for the IRQ map */
#define PNP_IRQ_FRMT			0x0022		/* PNP small item IRQ format */
#define CS8900_IRQ_MAP			0x1c20		/* This IRQ map is fixed */

#define CS8920_NO_INTS			0x0F		/* Max CS8920 interrupt select # */

#define PNP_ADD_PORT			0x0279
#define PNP_WRITE_PORT			0x0A79

#define GET_PNP_ISA_STRUCT		0x40
#define PNP_ISA_STRUCT_LEN		0x06
#define PNP_CSN_CNT_OFF			0x01
#define PNP_RD_PORT_OFF			0x02
#define PNP_FUNCTION_OK			0x00
#define PNP_WAKE				0x03
#define PNP_RSRC_DATA			0x04
#define PNP_RSRC_READY			0x01
#define PNP_STATUS				0x05
#define PNP_ACTIVATE			0x30
#define PNP_CNF_IO_H			0x60
#define PNP_CNF_IO_L			0x61
#define PNP_CNF_INT				0x70
#define PNP_CNF_DMA				0x74
#define PNP_CNF_MEM				0x48

#define CS8900_MULTICAST_ENTRIES	64
#define CS8900_LOOKAHEAD			34		/* ether_header + ip_header */


struct _crys8900_out_buf {
    uint16_t    status;
    uint16_t    length;
    uint8_t     data[1600];
};


typedef struct _nic_cs8900_ext {
	nic_config_t        cfg;                /* New libdrvr config structure */
	nic_stats_t         stats;              /* New libdrvr config structure */
	uint32_t 			iobase;
	int					chid;				/* channel id */
	int					coid;				/* connection id */
	int					tid;				/* thread id */
	int					iid;				/* interrupt id */
    io_net_self_t       *ion;
    void                *dll_hdl;
    int                 reg_hdl;
    uint16_t            cell;
	uint16_t			zero;
    unsigned            max_pkts;

	struct sigevent		event;				/* interrupt pulse event */
	pthread_mutex_t		mutex;
	npkt_t				*nhead;
	npkt_t				*ntail;

	int                 rx_active;
	int                 rx_max;    
	npkt_t              **rx_pktq;
	int 				num_rx_pkts;
    int                 rx_pidx;
    int                 rx_cidx;
	int					chip_id;
	int					mode;
	uint32_t 			duplex;
	int					auto_neg_cnf;
	int					adapter_cnf;
	int					isa_cnf;
	int					tx_bid;
	int					tx_active;
#ifdef __X86__
	int					smem_size;
	int					smem_addr;
	char				*smem;
	int					dmem_size;
	char				*dmem;
#endif
	char				*dmem_cptr;
/*	int					_8bit; */
	int					map_flag;
	int					istat;
	int                 multicast_counts[CS8900_MULTICAST_ENTRIES];
    struct _crys8900_out_buf out_buf;
} cs8900_dev_t;

int cs8900_setup_multicast( void *handle );
int cs8900_init( void *, dispatch_t *dpp, io_net_self_t *, char *options);
int cs8900_devctl( void *hdl, int dcmd, void *data, size_t size, union _io_net_dcmd_ret_cred *ret );
int cs8900_shutdown1( int, void *hdl );
int cs8900_shutdown2( int, void *hdl );
int cs8900_flush( int, void *hdl );
int cs8900_advertise(int reg_hdl, void *func_hdl);
int cs8900_send_packets( npkt_t *npkt, void * );
npkt_t *cs8900_alloc_npkt(void *handle, size_t size);
int cs8900_receive_complete(npkt_t *npkt, void *, void *);

int cs8900_receive( void *handle );
int cs8900_receive_cntrs( void *handle );
int cs8900_transmit_complete( void *handle );
int cs8900_load( void *handle );


int cs8900_rpktpage( int iobase, int portno );
void cs8900_wpktpage( int iobase, int portno, int value );
void *cs8900_driver_thread( void *data );
void *cs8900_alloc_nic( int ext_size );

int cs8900_register_device( void *handle, io_net_self_t *ion, void * );
int crys8900_detect( void *, io_net_self_t *, char *options );
void setup_8237( int mode, int chnl, paddr_t dptr, int cnt );
int cs8900_do_multicast (cs8900_dev_t *cs8900, struct _io_net_msg_mcast *msg, int *ret);

#define ion_rx_packets          cs8900->ion->tx_up
#define ion_register            cs8900->ion->reg
#define ion_deregister          cs8900->ion->dereg
#define ion_alloc               cs8900->ion->alloc
#define ion_free                cs8900->ion->free
#define ion_alloc_npkt          cs8900->ion->alloc_up_npkt
#define ion_mphys               cs8900->ion->mphys
#define ion_tx_complete         cs8900->ion->tx_done
#define ion_add_done            cs8900->ion->reg_tx_done


#endif