config.c

QNX ADS BSP code for i.MX27 chips

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $
 */


#include "mxcspi.h"


int mx21_cfg(void *hdl, spi_cfg_t *cfg)
{
	mx21_cspi_t	*mx21 = hdl;
	uint32_t	ctrl, i, p, div, drate;

	if (cfg == NULL)
		return 0;

	ctrl = cfg->mode & SPI_MODE_CHAR_LEN_MASK;
	if (ctrl > 32 || ctrl < 1)
		return 0;

	--ctrl;

	for (p = 2, i = 2; i <= 18; i++) {
		div = p << 1;

		if (i & 1) {
			div += p;
		    p <<= 1;
		}
		drate = mx21->clock / div;
		if (drate <= cfg->clock_rate) {
			cfg->clock_rate = drate;
			ctrl |= i << 14;
			break;
		}
	}

	if (i > 18)
		return 0;

	if (!(cfg->mode & SPI_MODE_CKPOL_HIGH))
		ctrl |= 1 << 5;		/* Active low polarity */

	if (cfg->mode & SPI_MODE_CKPHASE_HALF)
		ctrl |= 1 << 6;		/* Phase 1 */

	if (cfg->mode & SPI_MODE_CSPOL_HIGH)
		ctrl |= 1 << 8;		/* SS polarity : active high */

	switch (cfg->mode & SPI_MODE_RDY_MASK) {
		case SPI_MODE_RDY_EDGE:
			ctrl |= 1 << 12;
			break;
		case SPI_MODE_RDY_LEVEL:
			ctrl |= 2 << 12;
			break;
	}

	if (!(cfg->mode & SPI_MODE_IDLE_INSERT))
		ctrl |= 1 << 23;		/* No idle time between consecutive data transfers */

	if (cfg->mode & SPI_MODE_CSSTAT_HIGH)
		ctrl |= 1 << 7;			/* Insert CS pulse between CSPI burst */

	return ctrl;
}