pxa300.h

QNX ADS BSP code for i.MX27 chips

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */
/*
 * Marvell PXA300 Processor
 *
 *
 *
 */

#ifndef ARM_PXA300_H_INCLUDED
#define ARM_PXA300_H_INCLUDED

/*
 * -------------------------------------------------------------------------
 * Chip selects and memory banks
 * -------------------------------------------------------------------------
 */
#define PXA300_SCS0             (0x00000000)
#define PXA300_SCS1             (0x04000000)
#define PXA300_SCS2             (0x08000000)
#define PXA300_SCS3             (0x0C000000)
#define PXA300_SCS4             (0x10000000)
#define PXA300_SCS5             (0x14000000)
#define PXA300_SDRAM0           (0x80000000)
#define PXA300_SDRAM1           (0xC0000000)

/*
 * -------------------------------------------------------------------------
 * Static memory controller
 * -------------------------------------------------------------------------
 */
#define PXA300_SMEMC_BASE		0x4A000000

#define PXA300_MSC1				0x0c
#define PXA300_MEMCLKCFG		0x68
#define PXA300_CSADRCFG0		0x80
#define PXA300_CSADRCFG1		0x84
#define PXA300_CSADRCFG2		0x88
#define PXA300_CSADRCFG3		0x8C
#define PXA300_CSMSADRCFG		0xA0

/*
 * -------------------------------------------------------------------------
 * Multi-function Pin Registers
 * -------------------------------------------------------------------------
 */
#define PXA300_MFPR_BASE		0x40E10000

/*
 * TODO:
 * Offsets for MFPR functions used in Zylonite. Should be moved to the
 * Zylonite header file at a later date, and general MFPR definitions
 * kept here.
 */
#define PXA300_MFPR_SMEMC_RDY		0xB4
#define PXA300_MFPR_SMEMC_nCS2		0xB8
#define PXA300_MFPR_SMEMC_nCS3		0xBC

#define PXA300_MFPR_FFUART_RX		0x40C
#define PXA300_MFPR_FFUART_TX		0x410

#define PXA300_MFPR_DF_INT_RNB		0xC8
#define PXA300_MFPR_DF_NWE			0xCC
#define PXA300_MFPR_DF_NCS0			0x248
#define PXA300_MFPR_DF_NCS1			0x278
#define PXA300_MFPR_DF_NRE			0x200

#define PXA300_MFPR_DF_IO0			0x220
#define PXA300_MFPR_DF_IO1			0x228
#define PXA300_MFPR_DF_IO2			0x230
#define PXA300_MFPR_DF_IO3			0x238
#define PXA300_MFPR_DF_IO4			0x258
#define PXA300_MFPR_DF_IO5			0x260
#define PXA300_MFPR_DF_IO6			0x268
#define PXA300_MFPR_DF_IO7			0x270
#define PXA300_MFPR_DF_IO8			0x224
#define PXA300_MFPR_DF_IO9			0x22C
#define PXA300_MFPR_DF_IO10			0x234
#define PXA300_MFPR_DF_IO11			0x23C
#define PXA300_MFPR_DF_IO12			0x25C
#define PXA300_MFPR_DF_IO13			0x264
#define PXA300_MFPR_DF_IO14			0x26C
#define PXA300_MFPR_DF_IO15			0x274

#define PXA300_MFPR_ALE_nWE			0x20C
#define PXA300_MFPR_nLLA			0x254
#define PXA300_MFPR_nLUA			0x244
#define PXA300_MFPR_nBE0			0x204
#define PXA300_MFPR_nBE1			0x208
#define PXA300_MFPR_CLE_nOE			0x240

#define PXA300_MFPR_ENET_IRQ		0x600

/*
 * -------------------------------------------------------------------------
 * Slave Clock Control Unit
 * -------------------------------------------------------------------------
 */
#define PXA300_BCCU_BASE		0x41340000

#define PXA300_ACSR				0x04

/* Input clock */
#define PXTAL_IN	13000000


#endif