mmu.h

QNX ADS BSP code for i.MX27 chips

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $
 */

/*
 * ARM MMU (coprocessor 15) Support
 */

#ifndef	__ARM_MMU_H_INCLUDED
#define	__ARM_MMU_H_INCLUDED

/*
 * MMU control register
 */
#define	ARM_MMU_CR_M	(1 <<  0)	/* enable MMU */
#define	ARM_MMU_CR_A	(1 <<  1)	/* enable alignment faults */
#define	ARM_MMU_CR_C	(1 <<  2)	/* enable data/IDC cache */
#define	ARM_MMU_CR_W	(1 <<  3)	/* enable write buffer */
#define	ARM_MMU_CR_P	(1 <<  4)	/* 32-bit exception handling */
#define	ARM_MMU_CR_D	(1 <<  5)	/* 32-bit data address range */
#define	ARM_MMU_CR_L	(1 <<  6)	/* late aborts */
#define	ARM_MMU_CR_B	(1 <<  7)	/* big endian */
#define	ARM_MMU_CR_S	(1 <<  8)	/* system protection */
#define	ARM_MMU_CR_R	(1 <<  9)	/* ROM protection */
#define	ARM_MMU_CR_F	(1 << 10)	/* implementation defined */
#define	ARM_MMU_CR_Z	(1 << 11)	/* implementation defined */
#define	ARM_MMU_CR_I	(1 << 12)	/* enable instruction cache */
#define	ARM_MMU_CR_X	(1 << 13)	/* exception vector adjust */
#define	ARM_MMU_CR_RR	(1 << 14)	/* round robin cache replacement */
#define	ARM_MMU_CR_nF	(1 << 30)	/* not FastBus select */
#define	ARM_MMU_CR_iA	(1 << 31)	/* async clock select */

#define	ARM_L1_SIZE		16384
#define	ARM_L2_SIZE		1024
#define	PGMASK			(__PAGESIZE-1)

/*
 * Page/Section access permissions.
 * NB: assumes the MMU control register has been set with S=1,R=0
 */
#define	ARM_PTE_RO		0			/* read-only  access */
#define	ARM_PTE_RW		1			/* read-write access */
#define	ARM_PTE_U		2			/* user mode  access */
#define	ARM_PTE_AP_MASK	3

#define	ARM_PTE_B		4			/* bufferable */
#define	ARM_PTE_C		8			/* machine-dependent (see below) */
#define	ARM_PTE_CB		12			/* cacheable and bufferable */

/*
 * L1 descriptors
 */
typedef unsigned	ptp_t;
#define	ARM_PTP_L2		0x11
#define	ARM_PTP_SC		0x12
#define	ARM_PTP_VALID	3

/*
 * L2 descriptors
 */
typedef unsigned	pte_t;
#define	ARM_PTE_LP		1
#define	ARM_PTE_SP		2
#define	ARM_PTE_XSP		3			/* ARMv5 extended small page */
#define	ARM_PTE_VALID	3

#define	ARM_L2_TEX_MASK	0x1c0

#define	ARM_PTE_PROT(f)	(((f) << 4) | ((f) << 6) | ((f) << 8) | ((f) << 10))
#define	ARM_XSP_PROT(f)	((f) << 4)

#define	ARM_PTE_WT		ARM_PTE_C			/* write-thru (non-SA11x0) */
#define	ARM_PTE_WB		ARM_PTE_CB			/* write-back (all cores)  */
#define	ARM_PTE_SA_MC	ARM_PTE_C			/* mini-cache (SA11x0)     */

#define	ARM_PTE_XS_X	0x40						/* Xscale X-bit */
#define	ARM_PTE_XS_MC	(ARM_PTE_XS_X | ARM_PTE_C)	/* mini-cache (Xscale) */
#define	ARM_PTE_XS_WA	(ARM_PTE_XS_X | ARM_PTE_WB)	/* write-allocate */

/*
 * Address translation support.
 *
 * The virtual address space contains the following reserved regions:
 *	00000000-00000fff	trap vector table for processors without vector adjust
 *	ff800000-ffbfffff	maps page tables that map 00000000-ffffffff
 *	ffff0000-ffff0fff	trap vector table for processors with vector adjust
 *
 * The startup normally arranges the following mappings:
 *	fc400000-fdffffff	maps L1 page table and mappings for callouts
 *	fe000000-ff7fffff	maps boot programs (kdebug/procnto)
 */

#define	ARM_STARTUP_BASE	0xfc400000
#define	ARM_BOOTPGM_BASE	0xfe000000

#define	ARM_PTE_MAP			1022
#define	ARM_PTE_BASE		(ARM_PTE_MAP << 22)
#define	ARM_PTP_BASE		(ARM_PTE_BASE | (ARM_PTE_MAP << 12))

#define	VTOPDIR(v)	(ptp_t *)(ARM_PTP_BASE | (((unsigned)(v) >> 20) & ~3))
#define	VTOPTEP(v)	(pte_t *)(ARM_PTE_BASE | (((unsigned)(v) >> 10) & ~3))
#define	VTOPTP(v)	(pte_t *)(ARM_PTE_BASE | (((unsigned)(v) >> 10) & 0x3ff000))
#define	VTOP(v)		((*(VTOPTEP(v)) & ~PG_MASK) | ((unsigned)(v) & PG_MASK))

/*
 * --------------------------------------------------------------------------
 * Cache/TLB manipulation
 * --------------------------------------------------------------------------
 */

/*
 * Read the MMU control register
 */
static inline unsigned
arm_mmu_getcr()
{
	unsigned	val;
	__asm__ __volatile__(
		"mrc	p15, 0, %0, c1, c0, 0"
		: "=r" (val)
		:
	);
	return val;
}

/*
 * Flush the instruction and data TLBs
 */
static inline void
arm_v4_idtlb_flush()
{
	__asm__ __volatile__(
		"mcr	p15, 0, %0, c8, c7, 0"
		:
		: "r" (0)
	);
}

/*
 * Flush the data TLB by address
 */
static inline void
arm_v4_dtlb_addr(unsigned addr)
{
	__asm__ __volatile__(
		"mcr	p15, 0, %0, c8, c6, 1"
		:
		: "r" (addr)
	);
}

#endif	/* __ARM_MMU_H_INCLUDED */