arm_cores.c

QNX ADS BSP code for i.MX27 chips

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $
 */
 
 #include "startup.h"

/*
 * --------------------------------------------------------------------------
 * Currently known ARM cores
 * --------------------------------------------------------------------------
 */

const struct arm_core_info		arm_cores[] = {
	{
		0x7200,
		"arm720",
		&arm720_config,
		0
	},

	{
		0x9200,
		"arm920",
		&arm92x_config,
		arm920_extra_init
	},

	{
		0x9220,
		"arm922",
		&arm92x_config,
		arm920_extra_init
	},

	{
		0x9250,
		"arm925",
		&arm925_config,
		0
	},

	{
		0x9260,
		"arm926",
		&arm92x_config,
		0
	},

	{
		0xa200,
		"arm1020",
		&arm102x_config,
		0
	},

	{
		0xa220,
		"arm1022",
		&arm102x_config,
		0
	},

	{
		0xa110,
		"sa1100",
		&sa11x0_config,
		0
	},

	{
		0xb110,
		"sa1110",
		&sa11x0_config,
		0
	},

	{
		0xc120,
		"ixp1200",
		&ixp1200_config,
		0,
	},

	{
		0x2000,
		"i80200",
		&xscale_errata_config,
		xscale_extra_init
	},

	{
		0x2100,
		"pxa250",			// stepping A0/A1
		&xscale_errata_config,
		xscale_extra_init
	},

	{
		0x2900,
		"pxa250",			// stepping B0/B1/B2
		&xscale_errata_config,
		xscale_extra_init
	},

    {
        0x2d00,
        "pxa250",			// stepping C0
        &xscale_config,
        xscale_extra_init
    },

    {
        0x2920,
        "pxa210",			// stepping B0/B1/B2
        &xscale_errata_config,
        xscale_extra_init
    },

    {
        0x2d20,
        "pxa210",			// stepping C0
        &xscale_config,
        xscale_extra_init
    },

    {
        0x4110,
        "pxa270",
        &xscale_config,
        xscale_extra_init
    },

    {
        0x6880,
        "pxa300",			// Monahans L, stepping A0/A1
        &xscale_config,
        xscale_extra_init
    },

    {
        0x6890,
        "pxa310",			// Monahans LV, stepping A0/A1
        &xscale_config,
        xscale_extra_init
    },

	{
		0x4190,
		"ixp2400",
		&ixp2400_config,
		xscale_extra_init                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      
	},

	{
		0x41a0,
		"ixp2800",
		&xscale_config,
		xscale_extra_init                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      
	},

	{
		0x41c0,
		"ixp425",
		&xscale_config,
		xscale_extra_init,
	},

	{
		0x4200,
		"ixp465",
		&xscale_config,
		xscale_extra_init,
	},

	{
		0x6200,
		"ixp23xx",
		&ixp23xx_config,
		xscale_extra_init
	},	

	{
		0xb360,
		"arm1136",
		&arm1136_config,
		&arm1136_extra_init
	},

	{	0, 0, 0, 0 }
};

/*
 * --------------------------------------------------------------------------
 * CPU core configuration details
 * --------------------------------------------------------------------------
 */

const struct arm_core_config	arm720_config = {
		0,								// mmu_cr
		0,								// cycles
		&arm720_cache,					// cache
		0,								// power
		&page_flush_720,				// flush
		&page_flush_deferred_720,		// deferred
		&armv4_pte_info					// pte
};

const struct arm_core_config	arm92x_config = {
		ARM_MMU_CR_I | ARM_MMU_CR_RR,
		4,								// cycles
		&arm92x_cache,					// cache
		&power_920,						// power
		&page_flush_920,				// flush
		&page_flush_deferred_920,		// deferred
		&armv4_pte_info					// pte
};

const struct arm_core_config	arm925_config = {
		ARM_MMU_CR_I,
		4,								// cycles
		&arm925_cache,					// cache
		&power_920,						// power
		&page_flush_925,				// flush
		&page_flush_deferred_925,		// deferred
		&armv4_pte_info					// pte
};

const struct arm_core_config	arm102x_config = {
		ARM_MMU_CR_I | ARM_MMU_CR_Z | ARM_MMU_CR_RR,
		2,								// cycles
		&arm102x_cache,					// cache
		&power_920,						// power
		&page_flush_1020,				// flush
		&page_flush_deferred_1020,		// deferred
		&armv4_pte_info					// pte
};

const struct arm_core_config	sa11x0_config = {
		ARM_MMU_CR_I,
		3,								// cycles
		&sa11x0_cache,					// cache
		&power_sa1100,					// power
		&page_flush_sa,					// flush
		&page_flush_deferred_sa,		// deferred
		&armv4_pte_info					// pte
};

const struct arm_core_config	ixp1200_config = {
		ARM_MMU_CR_I,
		3,								// cycles
		&sa11x0_cache,					// cache
		0,								// power
		&page_flush_sa,					// flush
		&page_flush_deferred_sa,		// deferred
		&armv4_pte_info					// pte
};

const struct arm_core_config	xscale_errata_config =	{
		ARM_MMU_CR_I | ARM_MMU_CR_Z,
		2,								// cycles
		&xscale_cache,					// cache
		&power_xscale,					// power
		&page_flush_sa2,				// flush
		&page_flush_deferred_sa2,		// deferred
		&armv5_wb_pte_info				// pte
};

const struct arm_core_config	xscale_config =	{
		ARM_MMU_CR_I | ARM_MMU_CR_Z,
		2,								// cycles
		&xscale_cache,					// cache
		&power_xscale,					// power
		&page_flush_sa2,				// flush
		&page_flush_deferred_sa2,		// deferred
		&armv5_wa_pte_info				// pte
};

const struct arm_core_config	ixp2400_config =	{
		ARM_MMU_CR_I | ARM_MMU_CR_Z,
		2,								// cycles
		&xscale_cache,					// cache
		&power_xscale,					// power
		&page_flush_sa2,				// flush
		&page_flush_deferred_sa2,		// deferred
		&ixp2400_pte_info				// pte
};

const struct arm_core_config	ixp23xx_config =	{
		ARM_MMU_CR_I,
		2,								// cycles
		&xscale_cache,					// cache
		0,								// power
		&page_flush_sa2,				// flush
		&page_flush_deferred_sa2,		// deferred
		&ixp2400_pte_info				// pte
};

const struct arm_core_config	arm1136_config =	{
		ARM_MMU_CR_I | ARM_MMU_CR_Z,
		4,								// cycles	FIXME
		&arm1136_cache,					// cache
		0,								// power	FIXME
		&page_flush_1136,				// flush
		&page_flush_deferred_1136,		// deferred
		&armv4_pte_info					// pte
};

extern const struct arm_core_info	arm_bsp_cores[];

const struct arm_core_info *
arm_core_detect()
{
	const struct arm_core_info	*core;
	unsigned					cpuid;

	__asm__("mrc	p15, 0, %0, c0, c0, 0"
			: "=r" (cpuid)
			:
	);

	/*
	 * Check if the board specific startup contains additional cores
	 */
	for (core = arm_bsp_cores; core->cpuid; core++) {
		if (core->cpuid == (cpuid & 0xfff0)) {
			break;
		}
	}

	if (core->cpuid == 0) {
		/*
		 * Check the list of cores we know about
		 */
		for (core = arm_cores; core->cpuid; core++) {
			if (core->cpuid == (cpuid & 0xfff0)) {
				break;
			}
		}
	}

	if (core->cpuid == 0) {
		crash("Unsupported CPUID 0x%l\n", cpuid);
	}
	if (core->config == 0) {
		crash("No config for CPUID 0x%l\n", cpuid);
	}

	return core;
}