arm_pte.c

QNX ADS BSP code for i.MX27 chips

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $
 */
 
#include "startup.h"

/*
 * --------------------------------------------------------------------------
 * MMU PTE information
 * --------------------------------------------------------------------------
 */

/*
 * ARMv4 page table entries:
 *
 * - RO/RW pages both use default cached access
 * - uncached pages need to clear the CB bits
 *
 * This used by the following processors:
 * - ARM720
 * - ARM92x
 * - ARM102x
 */
const struct arm_pte_info	armv4_pte_info = {
	ARM_PTE_SP | ARM_PTE_PROT(ARM_PTE_RO|ARM_PTE_U) | ARM_PTE_CB,	// upte_ro
	ARM_PTE_SP | ARM_PTE_PROT(ARM_PTE_RW|ARM_PTE_U) | ARM_PTE_CB,	// upte_rw
	ARM_PTE_SP | ARM_PTE_PROT(ARM_PTE_RO)           | ARM_PTE_CB,	// kpte_ro
	ARM_PTE_SP | ARM_PTE_PROT(ARM_PTE_RW)           | ARM_PTE_CB,	// kpte_rw
	ARM_PTE_CB														// mask_nc
};

/*
 * for arm 925 core
 */

const struct arm_pte_info	armv4_wt_pte_info = {
	ARM_PTE_SP | ARM_PTE_PROT(ARM_PTE_RO|ARM_PTE_U) | ARM_PTE_WT,	// upte_ro
	ARM_PTE_SP | ARM_PTE_PROT(ARM_PTE_RW|ARM_PTE_U) | ARM_PTE_WT,	// upte_rw
	ARM_PTE_SP | ARM_PTE_PROT(ARM_PTE_RO)           | ARM_PTE_WT,	// kpte_ro
	ARM_PTE_SP | ARM_PTE_PROT(ARM_PTE_RW)           | ARM_PTE_WT,	// kpte_rw
	ARM_PTE_CB														// mask_nc
};

/*
 * ARMv5 Write-Allocate extended page table entries:
 *
 * - RO pages use default cached access
 * - RW pages use write-allocate caching
 * - uncached pages need to clear the X bit as well as the CB bits
 *
 * This is used by the following processors:
 * - pxa250 rev C0 and above
 * - pxa210 rev C0 and above
 */
const struct arm_pte_info	armv5_wa_pte_info = {
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RO|ARM_PTE_U) | ARM_PTE_CB,		// upte_ro
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RW|ARM_PTE_U) | ARM_PTE_XS_WA,	// upte_rw
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RO)           | ARM_PTE_CB,		// kpte_ro
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RW)           | ARM_PTE_XS_WA,	// kpte_rw
	ARM_PTE_XS_X | ARM_PTE_CB											// mask_nc
};

/*
 * ARMv5 Write-Back extended page table entries:
 *
 * - RO pages use write-through caching  (errata #17 workaround)
 * - RW pages use write-back caching (as was used in 6.1/6.2 release code)
 * - uncached pages need to clear the CB bits
 *
 * This is used to workaround errata in the following processors:
 * - pxa250 rev A0/A1/B0/B1/B2
 * - pxa210 rev B0/B1/B2
 * - 80200  rev A0/A1/B0/C0
 * - 80321  rev A0/B0
 */
const struct arm_pte_info	armv5_wb_pte_info = {
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RO|ARM_PTE_U) | ARM_PTE_WT,		// upte_ro
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RW|ARM_PTE_U) | ARM_PTE_CB,		// upte_rw
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RO)           | ARM_PTE_WT,		// kpte_ro
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RW)           | ARM_PTE_CB,		// kpte_rw
	ARM_PTE_XS_X | ARM_PTE_CB											// mask_nc
};

/*
 * ARMv5 Write-Through extended page table entries:
 *
 * - RO pages use write-through caching
 * - RW pages use write-through caching
 * - uncached pages need to clear the CB bits
 *
 * This is used to workaround errata in the following processors:
 * - pxa250 rev A0/A1/B0/B1/B2
 * - pxa210 rev B0/B1/B2
 * - 80200  rev A0/A1/B0/C0
 * - 80321  rev A0/B0
 */
const struct arm_pte_info	armv5_wt_pte_info = {
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RO|ARM_PTE_U) | ARM_PTE_WT,		// upte_ro
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RW|ARM_PTE_U) | ARM_PTE_WT,		// upte_rw
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RO)           | ARM_PTE_WT,		// kpte_ro
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RW)           | ARM_PTE_WT,		// kpte_rw
	ARM_PTE_XS_X | ARM_PTE_CB											// mask_nc
};

/*
 * ARMv5 extended page table entries for ixp2400 workaround
 *
 * - RO pages use default cached access
 * - RW pages use write-allocate caching
 * - uncached pages need to use X=1,C=0,B=1
 */
const struct arm_pte_info	ixp2400_pte_info = {
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RO|ARM_PTE_U) | ARM_PTE_CB,		// upte_ro
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RW|ARM_PTE_U) | ARM_PTE_XS_WA,	// upte_rw
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RO)           | ARM_PTE_CB,		// kpte_ro
	ARM_PTE_XSP  | ARM_XSP_PROT(ARM_PTE_RW)           | ARM_PTE_XS_WA,	// kpte_rw
	ARM_PTE_C															// mask_nc
};

/*
 * The following pointer can be set by a board specific startup program
 * to override the value specified by the arm_core_info for the CPU
 */
const struct arm_pte_info	*arm_pte_info;

void
arm_get_pte_info()
{
	const struct arm_core_info	*core;
	const struct arm_pte_info	*pte;
	struct arm_cpu_entry		*cpu = lsp.cpu.arm_cpu.p;

	if ((pte = arm_pte_info) == 0) {
		core = arm_core_detect();
		if (core->config->pte == 0) {
			crash("No pte descriptors for %s", core->name);
		}

		/*
		 * Check if -x overrides page table entries
		 */
		switch (arm_altpte) {
		case 'a':	pte = &armv5_wa_pte_info;
					break;

		case 'b':	pte = &armv5_wb_pte_info;
					break;

		case 't':	pte = &armv5_wt_pte_info;
					break;

		default:	pte = core->config->pte;
					break;
		}
		arm_pte_info = pte;
	}

	/*
	 * Set the arm_cpu fields
	 */
	cpu->upte_ro = pte->upte_ro;
	cpu->upte_rw = pte->upte_rw;
	cpu->kpte_ro = pte->kpte_ro;
	cpu->kpte_rw = pte->kpte_rw;
	cpu->mask_nc = pte->mask_nc;
}