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📄 callout_timer_mx1.s

📁 QNX ADS BSP code for i.MX27 chips
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#  # Copyright 2007, QNX Software Systems. #  # Licensed under the Apache License, Version 2.0 (the "License"). You # may not reproduce, modify or distribute this software except in # compliance with the License. You may obtain a copy of the License # at: http://www.apache.org/licenses/LICENSE-2.0 #  # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" basis, # WITHOUT WARRANTIES OF ANY KIND, either express or implied.# # This file may contain contributions from others, either as # contributors under the License or as licensors under other terms.  # Please review this entire file for other proprietary rights or license # notices, as well as the QNX Development Suite License Guide at # http://licensing.qnx.com/license-guide/ for other information.# /* * MC9328MX1 timer support */#include "callout.ah"#include <arm/mx1.h>/* * -------------------------------------------------------------------------- * Routine to patch callout code * * On entry: *	r0 - physical address of syspage *	r1 - virtual  address of syspage *	r2 - offset from start of syspage to start of the callout routine *	r3 - offset from start of syspage to read/write data used by callout * -------------------------------------------------------------------------- */patch_timer:	stmdb	sp!,{r4,lr}	add		r4, r0, r2					// address of callout routine	/*	 * Map registers	 */	mov		r0, #MX1_TIMER_SIZE			// size of registers	ldr		r1, Lpaddr	bl		callout_io_map	/*	 * Patch the callout routine	 */	CALLOUT_PATCH	r4, r0, r1, r2, ip	ldmia	sp!,{r4,pc}Lpaddr:	.word	MX1_TIMER1_BASE/* * -------------------------------------------------------------------------- * Set clock resolution, and enable interrupt triggering as a side effect. * The interrupt remains masked until it is enabled via intr_unmask_mx1 * * On entry: *	r0 - pointer to syspage_entry *	r1 - pointer to qtime_entry * -------------------------------------------------------------------------- */CALLOUT_START(timer_load_mx1, 0, patch_timer)	/*	 * Get the address of the timer registers (patched)	 */	mov		ip,     #0x000000ff	orr		ip, ip, #0x0000ff00	orr		ip, ip, #0x00ff0000	orr		ip, ip, #0xff000000	/*	 * Disable Timer 	 */	ldr		r0, [ip, #MX1_TIMER_CTL]	bic		r0, r0, #0x11	str		r0, [ip, #MX1_TIMER_CTL]	/*	 * load counter value	 */	ldr		r2, [r1, #QT_TIMER_LOAD]	str		r2, [ip, #MX1_TIMER_CMP]	/*	 * Restart Timer, Enable interrupt	 */	orr		r0, r0, #0x11	str		r0, [ip, #MX1_TIMER_CTL]	mov		pc, lrCALLOUT_END(timer_load_mx1)/* * -------------------------------------------------------------------------- * Read the current timer value, relative to the last clock tick * * On entry: *	r0 - pointer to syspage_entry *	r1 - pointer to qtime_entry * * FIXME: this doesn't deal with the counter wrapping, eg. ClockCycles just *		  at the point where the clock interrupt is triggerred. * -------------------------------------------------------------------------- */CALLOUT_START(timer_value_mx1, 0, patch_timer)	/*	 * Get the address of the timer registers (patched)	 */	mov		ip,     #0x000000ff	orr		ip, ip, #0x0000ff00	orr		ip, ip, #0x00ff0000	orr		ip, ip, #0xff000000	/*	 * Return current timer counter value	 */	ldr		r0, [ip, #MX1_TIMER_CN]	mov		pc, lrCALLOUT_END(timer_value_mx1)/* * -------------------------------------------------------------------------- * Clear timer interrupt. * * On entry: *	r0 - pointer to syspage_entry *	r1 - pointer to qtime_entry * -------------------------------------------------------------------------- */CALLOUT_START(timer_reload_mx1, 0, patch_timer)	/*	 * Get the address of the timer registers (patched)	 */	mov		ip,     #0x000000ff	orr		ip, ip, #0x0000ff00	orr		ip, ip, #0x00ff0000	orr		ip, ip, #0xff000000	/*	 * Clear status register 	 */	ldr		r0, [ip, #MX1_TIMER_STAT]	eor		r0, r0, #3	str		r0, [ip, #MX1_TIMER_STAT]	mov		pc, lrCALLOUT_END(timer_reload_mx1)

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