imx21.conf

QNX ADS BSP code for i.MX27 chips

# devg-imx21.so parameters for tailoring to specific displays 
# For more details on the required settings please consult the IMX21 reference
# manual and the documentation for your specific LCD.
#
# x		width of panel 
# y		height of panel
# mmio		MMIO register base
# tft		0 - LCD is passive display, 1 - LCD is active display
# color		0 - LCD is momochrome, 1 - LCD is color
# pbw		panel bus width: 0 = 1-bit, 2 = 4 bit, 3 = 8-bit
# pixpol	Pixel Polarity: 0 = active high, 1 = active low
# flmpol	First Line Marker: Polarity 0 = active high, 1 = active low
# lppol		Line Pilse Polarity: 0 = active high, 1 = active low
# clkpol	LCD Shift Clock Polarity: 0 = active negative edge of LSCLK, 1 = active positive edge of LSCLK
# oepol		Output Enable Polarity: 0 = active high, 1 = active low
# sclkidle	LSCLK Idle Enable: 0 = disable LSCLK, 1= enable LSCLK
# end_sel	Endian Select: 0 = little endian, 1 = big endian
# swap_sel	Swap Select, 0 = 16bpp, 12bpp mode, 1 = 8bpp, 4bpp, 2bpp, 1bpp mode
# rev_vs	Reverse Verdtical Scan: 0 = normal vertical scan, 1 = reverse vertical scan direction
# acdsel	ACD Clock Source Select: 0 = FRM, 1 = LP/HSYN 
# acd		Alternate Crystal Direction
# sclksel	LSCLK Select: 0 = disable OE & LSCLK in TFT mode when no data output, 1 = always enable LSCLK in TFT mode
# sharp		Setting for Sharp Configuratiom Register (set to 0 if not using Sharp LCD Config)
# pcd		Pixel Clock Divider
# hsw		Horizontal Sync Pulse Width (in SCLK periods)
# hw1		Wait Between OE and HSYNC (in SCLK periods)
# hw2		Wait Between HSYNC and Start of Next Line (in SCLK periods)
# vsw		Vertical Sync Pulse Width (in lines)
# vw1		Wait Between Frames 1 (in lines)
# vw2		Wait Between Frames 2 (in lines)
# con		LCDC PWM Contrast Control Register Setting
# dma		LCDC Graphic Window DMA Control Register Setting
# pa1		PA1 board (1 = PA1 0 = non-PA1 board)
#
# The driver will use the first un-commented entry.

# Sharp LQ035Q7DB02 LCD on M9328MX21ADS reference board (driver defaults)
x=240,y=320,mmio=0xcc800000,tft=1,color=1,pixpol=1,flmpol=0,lppol=0,clkpol=0,oepol=1,sclkidle=0,end_sel=0,swap_sel=0,rev_vs=0,sclksel=1,acdsel=0,sharp=0x120300,pcd=8,hsw=2,hw1=16,hw2=9,vsw=1,vw1=9,vw2=7,con=0xa903ff,dma=0x20008,pa1=0

# INNOLUX LCD on Cognac Development Board Rev 1.40
#x=320,y=240,mmio=0xcc800000,tft=1,color=1,pixpol=0,flmpol=1,lppol=1,clkpol=0,oepol=1,sclkidle=1,end_sel=0,swap_sel=0,rev_vs=1,sclksel=1,acdsel=1,sharp=0,pcd=6,hsw=17,hw1=12,hw2=107,vsw=4,vw1=8,vw2=9,con=0,dma=0x40008,pa1=0

# CHILLIN LCD on Cognac Development Board Rev 1.4
#x=320,y=240,mmio=0xcc800000,tft=1,color=1,pixpol=0,flmpol=1,lppol=1,clkpol=0,oepol=0,sclkidle=1,end_sel=0,swap_sel=0,rev_vs=1,sclksel=1,acdsel=1,sharp=0,pcd=5,hsw=29,hw1=30,hw2=31,vsw=4,vw1=8,vw2=8,con=0,dma=0x40008,pa1=0

# INNOXLUX LCD on PA1 Board
#x=320,y=240,mmio=0xcc800000,tft=1,color=1,pixpol=0,flmpol=1,lppol=1,clkpol=0,oepol=0,sclkidle=1,end_sel=0,swap_sel=0,rev_vs=1,sclksel=1,acdsel=1,sharp=0,pcd=4,hsw=17,hw1=12,hw2=107,vsw=4,vw1=8,vw2=9,con=0,dma=0x40008,pa1=1