📄 spi.lis
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.module spi.c
.area text(rom, con, rel)
0000 .dbfile E:\ICCAVR\icc\stk500\avrasp\spi.c
0000 .dbfunc e spi_enable _spi_enable fV
0000 ; i -> R20
.even
0000 _spi_enable::
0000 00D0 rcall push_gset1
0002 .dbline -1
0002 .dbline 11
0002 ; /** \file
0002 ; <b>SPI</b><br>
0002 ; Autor: Matthias Wei遝r<br>
0002 ; Copyright 2005: Matthias Wei遝r<br>
0002 ; License: QPL (see license.txt)
0002 ; <hr>
0002 ; */
0002 ; #include "stk500.h"
0002 ;
0002 ; void spi_enable(void)
0002 ; {
0002 .dbline 14
0002 ; unsigned char i;
0002 ;
0002 ; R_RES_ON;
0002 8BEF ldi R24,-5
0004 9FEF ldi R25,-1
0006 25B0 in R2,0x5
0008 2822 and R2,R24
000A 25B8 out 0x5,R2
000C .dbline 15
000C ; wait_ms(2);
000C 02E0 ldi R16,2
000E 10E0 ldi R17,0
0010 00D0 rcall _wait_ms
0012 .dbline 16
0012 ; PORTB &= BIT3_NEG & BIT5_NEG; //MOSI und SCK low
0012 8FED ldi R24,-33
0014 9FEF ldi R25,-1
0016 E7EF ldi R30,-9
0018 FFEF ldi R31,-1
001A E823 and R30,R24
001C 25B0 in R2,0x5
001E 2E22 and R2,R30
0020 25B8 out 0x5,R2
0022 .dbline 17
0022 ; DDRB |= BIT3_POS | BIT5_POS; //MOSI und SCK als Ausgang
0022 84B1 in R24,0x4
0024 8862 ori R24,40
0026 84B9 out 0x4,R24
0028 .dbline 18
0028 ; SPCR = 0x51; //SPI Master /16
0028 81E5 ldi R24,81
002A 8CBD out 0x2c,R24
002C .dbline 19
002C ; R_RES_OFF;
002C 2A9A sbi 0x5,2
002E .dbline 20
002E 4427 clr R20
0030 02C0 rjmp L6
0032 L3:
0032 .dbline 20
0032 0000 nop
0034 L4:
0034 .dbline 20
0034 4395 inc R20
0036 L6:
0036 .dbline 20
0036 ; for(i=0;i<200;i++) asm("nop");
0036 483C cpi R20,200
0038 E0F3 brlo L3
003A .dbline 21
003A ; R_RES_ON;
003A 8BEF ldi R24,-5
003C 9FEF ldi R25,-1
003E 25B0 in R2,0x5
0040 2822 and R2,R24
0042 25B8 out 0x5,R2
0044 .dbline 22
0044 ; wait_ms(2);
0044 02E0 ldi R16,2
0046 10E0 ldi R17,0
0048 00D0 rcall _wait_ms
004A .dbline 25
004A ;
004A ; //spi_set_speed(eeprom_read_byte(&eeprom_sck_period));
004A ; spi_set_speed(eeprom_sck_period);
004A 00910000 lds R16,_eeprom_sck_period
004E 18D0 rcall _spi_set_speed
0050 .dbline -2
0050 L2:
0050 00D0 rcall pop_gset1
0052 .dbline 0 ; func end
0052 0895 ret
0054 .dbsym r i 20 c
0054 .dbend
0054 .dbfunc e spi_disable _spi_disable fV
.even
0054 _spi_disable::
0054 .dbline -1
0054 .dbline 29
0054 ; }
0054 ;
0054 ; void spi_disable(void)
0054 ; {
0054 .dbline 30
0054 ; SPCR=0x00; //SPI aus
0054 2224 clr R2
0056 2CBC out 0x2c,R2
0058 .dbline 31
0058 ; DDRB &= BIT3_NEG & BIT5_NEG; //MOSI und SCK als Eingang (hochohmig)
0058 8FED ldi R24,-33
005A 9FEF ldi R25,-1
005C E7EF ldi R30,-9
005E FFEF ldi R31,-1
0060 E823 and R30,R24
0062 24B0 in R2,0x4
0064 2E22 and R2,R30
0066 24B8 out 0x4,R2
0068 .dbline 32
0068 ; R_RES_OFF;
0068 2A9A sbi 0x5,2
006A .dbline -2
006A L7:
006A .dbline 0 ; func end
006A 0895 ret
006C .dbend
006C .dbfunc e spi_reset _spi_reset fV
.even
006C _spi_reset::
006C .dbline -1
006C .dbline 36
006C ; }
006C ;
006C ; void spi_reset(void)
006C ; {
006C .dbline 37
006C ; R_RES_OFF;
006C 2A9A sbi 0x5,2
006E .dbline 38
006E ; wait_ms(2);
006E 02E0 ldi R16,2
0070 10E0 ldi R17,0
0072 00D0 rcall _wait_ms
0074 .dbline 39
0074 ; R_RES_ON;
0074 8BEF ldi R24,-5
0076 9FEF ldi R25,-1
0078 25B0 in R2,0x5
007A 2822 and R2,R24
007C 25B8 out 0x5,R2
007E .dbline -2
007E L8:
007E .dbline 0 ; func end
007E 0895 ret
0080 .dbend
0080 .dbfunc e spi_set_speed _spi_set_speed fV
0080 ; s -> R16
.even
0080 _spi_set_speed::
0080 00D0 rcall push_gset1
0082 .dbline -1
0082 .dbline 56
0082 ; }
0082 ;
0082 ; /**
0082 ; Stellt die Geschwindigkeit des SPI-Busses ein (bei f=8MHz)
0082 ; 0: /2 4MHz --SPI2X
0082 ; 1 /4 2MHz
0082 ; 2: /8 1MHz --SPI2X
0082 ; 3 /16 500kHz
0082 ; 4: /32 250kHz --SPI2X
0082 ; 5 /64 125kHz
0082 ; 6: /128 62,5kHz
0082 ;
0082 ; weitere Geschwindigkeiten geplant
0082 ; -> dann per Software-SPI
0082 ; */
0082 ; void spi_set_speed(unsigned char s)
0082 ; {
0082 .dbline 57
0082 0023 tst R16
0084 21F0 breq L13
0086 0230 cpi R16,2
0088 11F0 breq L13
008A 0430 cpi R16,4
008C 21F4 brne L10
008E L13:
008E .dbline 57
008E 8DB5 in R24,0x2d
0090 8160 ori R24,1
0092 8DBD out 0x2d,R24
0094 03C0 rjmp L11
0096 L10:
0096 .dbline 57
0096 ; if((s==0)||(s==2)||(s==4)) SPSR|=1; else SPSR&=0xFE;
0096 8DB5 in R24,0x2d
0098 8E7F andi R24,254
009A 8DBD out 0x2d,R24
009C L11:
009C .dbline 59
009C ;
009C ; switch(s)
009C 402F mov R20,R16
009E 5527 clr R21
00A0 4030 cpi R20,0
00A2 4507 cpc R20,R21
00A4 C9F0 breq L17
00A6 X0:
00A6 4130 cpi R20,1
00A8 E0E0 ldi R30,0
00AA 5E07 cpc R21,R30
00AC A9F0 breq L17
00AE 4230 cpi R20,2
00B0 E0E0 ldi R30,0
00B2 5E07 cpc R21,R30
00B4 A9F0 breq L18
00B6 4330 cpi R20,3
00B8 E0E0 ldi R30,0
00BA 5E07 cpc R21,R30
00BC 89F0 breq L18
00BE 4430 cpi R20,4
00C0 E0E0 ldi R30,0
00C2 5E07 cpc R21,R30
00C4 A1F0 breq L19
00C6 4530 cpi R20,5
00C8 E0E0 ldi R30,0
00CA 5E07 cpc R21,R30
00CC 81F0 breq L19
00CE 4630 cpi R20,6
00D0 E0E0 ldi R30,0
00D2 5E07 cpc R21,R30
00D4 99F0 breq L20
00D6 16C0 rjmp L14
00D8 X1:
00D8 .dbline 60
00D8 ; {
00D8 L17:
00D8 .dbline 63
00D8 ; case 0:
00D8 ; case 1:
00D8 ; SPCR&=0xFC;
00D8 8CB5 in R24,0x2c
00DA 8C7F andi R24,252
00DC 8CBD out 0x2c,R24
00DE .dbline 64
00DE ; break;
00DE 15C0 rjmp L15
00E0 L18:
00E0 .dbline 67
00E0 ; case 2:
00E0 ; case 3:
00E0 ; SPCR&=0xFC;
00E0 8CB5 in R24,0x2c
00E2 8C7F andi R24,252
00E4 8CBD out 0x2c,R24
00E6 .dbline 68
00E6 ; SPCR|=0x01;
00E6 8CB5 in R24,0x2c
00E8 8160 ori R24,1
00EA 8CBD out 0x2c,R24
00EC .dbline 69
00EC ; break;
00EC 0EC0 rjmp L15
00EE L19:
00EE .dbline 72
00EE ; case 4:
00EE ; case 5:
00EE ; SPCR&=0xFC;
00EE 8CB5 in R24,0x2c
00F0 8C7F andi R24,252
00F2 8CBD out 0x2c,R24
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