ha_emi.c

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	i = (U32)(size << 14);
	j=i+0x249B;                                                         //suradd and desadd not add up
	*(RP)tempcontrol = j;
	
	*(RP)tempconfig =0x31d;						//channel enable!
	
	
	*(RP)EMIADDR_NANDCOM = 0x80000000;					//write begin!
	
	#ifndef RELEASE
	i = *(RP)EMIADDR_NANDCOM;
	if( i!= 0x0000001 )
	{
		HA_EMI_WRIT(gloabalvar_add,EMIADDR_NANDCOM);
		gloabalvar_add = gloabalvar_add + 4;
	}
	#endif
	

	
	i = *(RP)EMIADDR_NANDIDLE;                         //judge Nand flash compish actions
	while((i&0x1) != 0x1)
	{  i = *(RP)EMIADDR_NANDIDLE; }
	
	
	
   return gloabalvar_add;
    
}


U32 Dma_Nand_Erase(U32 nand_Add, U32 gloabalvar_add)
{
	U32 i;
	*(RP)EMIADDR_NANDCONF = 0x0100aaa;                              //3 addresss mode
	#ifndef RELEASE
	i = *(RP)EMIADDR_NANDCONF;
	if( i!= 0x02000aaa )
	{
		HA_EMI_WRIT(gloabalvar_add,EMIADDR_NANDCONF);
		gloabalvar_add = gloabalvar_add + 4;
	}
	#endif
	
	*(RP)EMIADDR_NANDADDR = (nand_Add >> 8);
	#ifndef RELEASE
	i = *(RP)EMIADDR_NANDADDR;
	if( i!= (nand_Add >> 8))
	{
		HA_EMI_WRIT(gloabalvar_add, EMIADDR_NANDADDR);
		gloabalvar_add = gloabalvar_add + 4;
	}
	#endif
	
	
	*(RP)EMIADDR_NANDCOM = 0x80000060;
	#ifndef RELEASE
	i = *(RP)EMIADDR_NANDCOM;
	if( i!= 0x80000060 )
	{
		HA_EMI_WRIT(gloabalvar_add, EMIADDR_NANDCOM);
		gloabalvar_add = gloabalvar_add + 4;
	}
	#endif	
	
	
	i = *(RP)EMIADDR_NANDIDLE;                         //judge Nand flash compish actions
	while((i&0x1) != 0x1)
	{  i = *(RP)EMIADDR_NANDIDLE; }
	
	return gloabalvar_add;
}	





U32 Dma_Nand_StatusRead(U32 gloabalvar_add)
{
	U32 i;
                                            
	*(RP)EMIADDR_NANDCONF = EMIADDR_NANDCONF_VAL;                    //re_config
	#ifndef RELEASE
	i = *(RP)EMIADDR_NANDCONF;
	if( i!= EMIADDR_NANDCONF_VAL )
	{
		HA_EMI_WRIT(gloabalvar_add, EMIADDR_NANDCONF);
		gloabalvar_add = gloabalvar_add + 4;
	}
	#endif
	
	*(RP)EMIADDR_NANDCOM = 0x80000070;                               //read status command
	#ifndef RELEASE
	i = *(RP)EMIADDR_NANDCOM;
	if( i!= 0x80000070 )
	{
		HA_EMI_WRIT(gloabalvar_add, EMIADDR_NANDCOM);
		gloabalvar_add = gloabalvar_add + 4;
	}
	#endif	
	
	i = *(RP)EMIADDR_NANDSTATUS;	   	
        while((i&0x100) != 1)
	{
		i = *(RP)EMIADDR_NANDSTATUS;
	}

   	/////////////////read status end//////////////////////// 
   	
   	
   	
   	
   	
   	
   	
	return gloabalvar_add;
}



/*
ER HA_NandFlash(void)
{
	U32 i,j,k,p;
	U8 q,r;
	j = 0x28060000;                                                  //int error base
	
    i = *(RP)EMIADDR_NANDIDLE;                                       //wait till nand idle 
	while(i != 0x0)                                                  //0x0 represent idle
	{
	    i = *(RP)EMIADDR_NANDIDLE;
	}
	
   	k =( *(RP)EMIADDR_NANDCOM) & 0xff;	
   	
   	if( k == 0x80)
   	{
   		HA_NandFlash_BadBlcokHandler();
   	}
   	else if( k == 0x60)
   	{
   		HA_NandFlash_BadBlcokHandler();
   	}
   	else if( k == 0x00 )
   	{
   		i = *(RP)DMACdesAdd - 0x80;                             //find init address fo DMA trans
   		p = *(RP)EMIADDR_NANDERRORADDR1 + i;                    //find actual error address
   		q = *(RP)EMIADDR_NANDERRORADDR2 & 0xf;
   		r = 0x1;	
   		while(q != 0x1)
   		{
   			r = r <<1 ;
   			q = q -0x1;
   		}
   		
   		i = (      ((*(RP8)p ) & (~r))   |  (( ~ ((*(RP8)p ) & r)) & r)    )   ;
   		              
                *(RP8)p = i;                                             //correct bit write back to error adress
         }
      
    	*(RP)EMIADDR_NANDINTR = 0xff;                                    //clean int
   
    	return 0;
    	
}
   
   
   
   
   
   
U32 HA_NandFlash_IdRead(U32 gloabalvar_add)  
{
	
	U32 i;
                                            
	*(RP)EMIADDR_NANDCONF = EMIADDR_NANDCONF_VAL;                    //re_config
	#ifndef RELEASE
	i = *(RP)EMIADDR_NANDCONF;
	if( i!= EMIADDR_NANDCONF_VAL )
	{
		HA_EMI_WRIT(gloabalvar_add, EMIADDR_NANDCONF);
		gloabalvar_add = gloabalvar_add + 4;
	}
	#endif
	
	*(RP)EMIADDR_NANDCOM = 0x80000090;                               //read status command
	#ifndef RELEASE
	i = *(RP)EMIADDR_NANDCOM;
	if( i!= 0x80000090 )
	{
		HA_EMI_WRIT(gloabalvar_add, EMIADDR_NANDCOM);
		gloabalvar_add = gloabalvar_add + 4;
	}
	#endif	
	
	*(RP)0x58003f00 = *(RP)EMI_NAND_DATA;                                          //read ID

   	/////////////////read ID end//////////////////////// 
   	
   	i = *(RP)EMIADDR_NANDIDLE;                         //judge Nand flash compish actions
	while((i&0x1) != 0x1)
	{  i = *(RP)EMIADDR_NANDIDLE; }
	
	
   	*(RP)0x58003f00 = *(RP)EMI_NAND_DATA;                                          //read ID
   	
   	
	return gloabalvar_add;
}
 
   
   
   */
   
   
ER HA_NandFlash_BadBlcokHandler(void)
{
	return 0;
}	



U32 Nand_Reset(U32 gloabalvar_add)               
{                                                                               
	U32 i;  

	
	*(RP)EMIADDR_NANDCOM = 0x800000ff;					
	#ifndef RELEASE
	i = *(RP)EMIADDR_NANDCOM;
	if( i!= 0x000000ff )
	{
		HA_EMI_WRIT(gloabalvar_add,EMIADDR_NANDCOM);
		gloabalvar_add = gloabalvar_add + 4;
	}
	#endif
	
	
	i = *(RP)EMIADDR_NANDIDLE;                         //judge Nand flash compish actions
	while((i&0x1) != 0x1)
	{  i = *(RP)EMIADDR_NANDIDLE; }
	
	
   return gloabalvar_add;
    
}	







////////////////////////////////////////////////////Nor flash /////////////////////////////////////////////////
ER NorFlash_clearSR(void)
{
	*(RP)0x0000000 = 0x500050;
	return 1;
}




ER NorFlash_idlejud(U32 address)
{
	U32 temp;
	
	*(RP)address = 0x700070;
	temp = *(RP)address;
	while( temp != 0x800080 )
	{
		temp = *(RP)address ;
	}
	return 1;
}
	
	
ER NorFlash_Normal(U32 address)
{
	U32 temp;
	*(RP)address = 0xff00ff;
	//temp = NorFlash_idlejud(address);
	return 1;
}





ER NorFlash_unlock( U32 address)
{
	U32 temp;
	
	*(RP)address = 0x600060;
	
	
	*(RP)address = 0xd000d0;
		
	temp = NorFlash_idlejud(address);
	return 1;
}



ER NorFlash_bolckerase(U32 blockadd)
{
	U32 temp;
	
	*(RP)blockadd = 0x200020;
	*(RP)blockadd = 0xd000d0;
	
	temp = NorFlash_idlejud(blockadd);
	
	temp = NorFlash_clearSR( );			       //Clear SR
	return 1;
}


ER NorFlash_read( U32 address)
{
	U32 temp,i;
	
	//*(RP)address = 0xff;
	//*(RP)address = 0x200020;
	//*(RP)address = 0xd000d0;
	
	i = *(RP)address;
	
	temp = NorFlash_idlejud(address);
	
	printf("return of read is 0x%x", i);
	return i;
}



ER NorFlash_write( U32 Pageadd, U32 data )
{
	U32 temp;
		
	*(RP)Pageadd = 0x400040;
	*(RP)Pageadd = data;
	
	temp = NorFlash_idlejud(Pageadd);
	return 1;
}