📄 ha_emi.c
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/*
**************************************************************************************************************************
*filename: HA_EMI.C
*author: XIAOJ
*create date: 2003-7-10 12:45
*description: The file consists of some functions of sram, sdram and Nand Flash
*modify history:
*misc:
*****************************************************************************************************************************
*/
#include "HA_TypeDef.h"
#include "hardware.h"
#include "hardware_reg.h"
U32 HA_INIT_EMI(U32 gloabalvar_add)
{
U32 temp;
*(RP)EMIADDR_CSGBAB = EMIADDR_CSGBAB_val;
*(RP)EMIADDR_CSGBCD = EMIADDR_CSGBCD_val;
*(RP)EMIADDR_CSGBEF = EMIADDR_CSGBEF_val;
*(RP)EMIADDR_SMCONF = EMIADDR_SMCONF_val;
*(RP)EMIADDR_SDCONF1 = EMIADDR_SDCONF1_val;
*(RP)EMIADDR_SDCONF2 = EMIADDR_SDCONF2_val; //Initialization complished;
#if 0
temp = *(RP)EMIADDR_CSGBAB;
if(temp != EMIADDR_CSGBAB_val)
{
HA_EMI_WRIT(gloabalvar_add, EMIADDR_CSGBAB);
gloabalvar_add +=4;
return 1;
}
temp = *(RP)EMIADDR_CSGBCD;
if(temp != EMIADDR_CSGBCD_val)
{
HA_EMI_WRIT(gloabalvar_add, EMIADDR_CSGBCD);
gloabalvar_add +=4;
return 1;
}
temp = *(RP)EMIADDR_CSGBEF;
if(temp != EMIADDR_CSGBEF_val)
{
HA_EMI_WRIT(gloabalvar_add, EMIADDR_CSGBEF);
gloabalvar_add +=4;
return 1;
}
temp = *(RP)EMIADDR_SMCONF;
if(temp != EMIADDR_SMCONF_val)
{
HA_EMI_WRIT(gloabalvar_add, EMIADDR_SMCONF);
gloabalvar_add +=4;
return 1;
}
temp = *(RP)EMIADDR_SDCONF1;
if(temp != EMIADDR_SDCONF1_val)
{
HA_EMI_WRIT(gloabalvar_add, EMIADDR_SDCONF1);
gloabalvar_add +=4;
return 1;
}
temp = *(RP)EMIADDR_SDCONF2;
if(temp != EMIADDR_SDCONF2_val)
{
HA_EMI_WRIT(gloabalvar_add, EMIADDR_SDCONF2);
gloabalvar_add +=4;
return 1;
}
#endif
return gloabalvar_add;
}
ER HA_DMA_DATADEFINE(U32 beginadd, U32 num, U32 size) //define a source data area,prepare to be tranfered or compared
{
U32 i; //Write (num) WORD from the start address gvined
if(size == 0x8)
{
for(i = 0x0; i < num; i = i + 1 )
{
*(RP8)beginadd =( (0x01 + i*0x01) & 0xff );
beginadd = beginadd + 1;
}
}
else if(size == 0x16)
{
for(i = 0x0; i < num; i = i + 1 )
{
*(RP16)beginadd = ((0x0201 + i*0x0101*2) & 0xffff );
beginadd = beginadd + 2;
}
}
else if(size == 0x32)
{
for(i = 0x0; i < num; i = i + 1 )
{
*(RP)beginadd = ((0x04030201 + i*0x01010101*4) & 0xffffffff);
beginadd = beginadd + 4;
}
}
return 0;
}
U32 HA_DMA_DATADCHECK(U32 beginadd, U32 num, U32 size, U32 gloabalvar_add) //Check data area
{
U32 i; //read (num) WORD from the start address gvined
if(size == 0x8)
{
for(i = 0x0; i < num; i = i + 1 )
{
if(*(RP8)beginadd != ((0x01 + i*0x01) & 0xff) )
{
*(RP)gloabalvar_add = beginadd;
beginadd = beginadd + 1;
gloabalvar_add = gloabalvar_add + 4;
}
else beginadd = beginadd + 1;
}
}
else if(size == 0x16)
{
for(i = 0x0; i < num; i = i + 1 )
{
if( *(RP16)beginadd != ((0x0201 + i*0x0101*2) & 0xffff) )
{
*(RP)gloabalvar_add = beginadd;
beginadd = beginadd + 2;
gloabalvar_add = gloabalvar_add + 4;
}
else beginadd = beginadd + 2;
}
}
else if(size == 0x32)
{
for(i = 0x0; i < num; i = i + 1 )
{
if(*(RP)beginadd !=( (0x04030201 + i*0x01010101*4) & 0xffffffff) )
{
*(RP)gloabalvar_add = beginadd;
beginadd = beginadd + 4;
gloabalvar_add = gloabalvar_add + 4;
}
else beginadd = beginadd + 4;
}
}
return gloabalvar_add;
}
ER clear(U32 tempadd, U32 num)
{
U32 j;
for(j = 0x0; j < num; j = j+1 )
{
*(RP)tempadd = 0x0;
tempadd = tempadd + 4;
}
return 1;
}
ER HA_DMA_DATADCHECK_RECORD(U32 beginadd, U32 num, U32 gloabalvar_add)
//Check data area and record adresses to error area(from 0x28002000)
{ // NOTE: gloabalvar_add: gloabalvar address!!!!!
U32 i; //read (num) WORD from the start address gvined
for(i = 0x0; i < num; i = i + 1 )
{
if(*(RP)beginadd != 0x04030201 + i*0x01010101*4)
{
*(RP)gloabalvar_add = beginadd;
beginadd = beginadd + 4;
gloabalvar_add +=4;
}
else beginadd = beginadd + 4;
}
return 0;
}
ER HA_EMI_WRIT(U32 add, U32 data)
{
*(RP)add = data;
add += 4;
return 0;
}
U32 HA_INIT_NANDFLASH(U32 gloabalvar_add)
{
U32 i;
*(RP)EMIADDR_NANDCONF = EMIADDR_NANDCONF_VAL;
#ifndef RELEASE
i = *(RP)EMIADDR_NANDCONF;
if( i!= EMIADDR_NANDCONF_VAL )
{
HA_EMI_WRIT(gloabalvar_add,EMIADDR_NANDCONF);
}
#endif
return gloabalvar_add;
}
//////////////////////////// NEW DMAC for Nand Flash ////////////////////////xiaoj 2003.8.8 16:30
U32 Dma_Nand_Write(U32 nand_Add, U32 Dma_sur_Add, U32 size, U32 channelnum, U32 gloabalvar_add) //just burst size = 4;
{
U32 i,j;
U32 tempsrc,tempdest,tempcontrol,tempconfig; //These 4 temp regiser address rariable are used to replase registers
// of registers of channel which is used now
i = channelnum;
tempsrc = DMACbase + 0x1000 + i*0x100; //replase registers of channel to be used;
tempdest = DMACbase + 0x1004 + i*0x100;
tempcontrol = DMACbase + 0x100c + i*0x100;
tempconfig = DMACbase + 0x1010 + i*0x100;
//size:num of word,should be muiltpy of 16(words)
*(RP)EMIADDR_NANDCONF = EMIADDR_NANDCONF_VAL;
#ifndef RELEASE
i = *(RP)EMIADDR_NANDCONF;
if( i!= EMIADDR_NANDCONF_VAL )
{
HA_EMI_WRIT(gloabalvar_add,EMIADDR_NANDCONF);
gloabalvar_add = gloabalvar_add + 4;
}
#endif
*(RP)EMIADDR_NANDADDR = nand_Add;
#ifndef RELEASE
i = *(RP)EMIADDR_NANDADDR;
if( i!= nand_Add )
{
HA_EMI_WRIT(gloabalvar_add,EMIADDR_NANDADDR);
gloabalvar_add = gloabalvar_add + 4;
}
#endif
*(RP)tempsrc = Dma_sur_Add;
*(RP)tempdest = EMI_NAND_DATA;
i = (U32)(size << 14);
j=i+0x149B; //suradd and desadd not add up
*(RP)tempcontrol = j;
*(RP)tempconfig =0x301b; //channel enable!
*(RP)EMIADDR_NANDCOM = 0x80000080; //write begin!
#ifndef RELEASE
i = *(RP)EMIADDR_NANDCOM;
if( i!= 0x0000001 )
{
HA_EMI_WRIT(gloabalvar_add,EMIADDR_NANDCOM);
gloabalvar_add = gloabalvar_add + 4;
}
#endif
i = *(RP)EMIADDR_NANDIDLE; //judge Nand flash compish actions
while((i&0x1) != 0x1)
{ i = *(RP)EMIADDR_NANDIDLE; }
return gloabalvar_add;
}
U32 Dma_Nand_Read(U32 nand_Add, U32 Dma_des_Add, U32 size, U32 channelnum, U32 gloabalvar_add) //just burst size = 4;
{ //size:num of word,should be muiltpy of 16(words)
U32 i,j;
U32 tempsrc,tempdest,tempcontrol,tempconfig; //These 4 temp regiser address rariable are used to replase registers
// of registers of channel which is used now
i = channelnum;
tempsrc = DMACbase + 0x1000 + i*0x100; //replase registers of channel to be used;
tempdest = DMACbase + 0x1004 + i*0x100;
tempcontrol = DMACbase + 0x100c + i*0x100;
tempconfig = DMACbase + 0x1010 + i*0x100;
//size:num of word,should be muiltpy of 16(words)
*(RP)EMIADDR_NANDCONF = EMIADDR_NANDCONF_VAL;
#ifndef RELEASE
i = *(RP)EMIADDR_NANDCONF;
if( i!= EMIADDR_NANDCONF_VAL )
{
HA_EMI_WRIT(gloabalvar_add,EMIADDR_NANDCONF);
gloabalvar_add = gloabalvar_add + 4;
}
#endif
*(RP)EMIADDR_NANDADDR = nand_Add;
#ifndef RELEASE
i = *(RP)EMIADDR_NANDADDR;
if( i!= nand_Add )
{
HA_EMI_WRIT(gloabalvar_add,EMIADDR_NANDADDR);
gloabalvar_add = gloabalvar_add + 4;
}
#endif
*(RP)tempsrc = EMI_NAND_DATA;
*(RP)tempdest = Dma_des_Add ;
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