vc1dsp.mid

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	.file	1 "vc1dsp.c"
	.section .mdebug.abi32
	.previous
	.section	.text.vc1_v_overlap_c,"ax",@progbits
	.align	2
	.align	5
	.ent	vc1_v_overlap_c
	.type	vc1_v_overlap_c, @function
vc1_v_overlap_c:
	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
	.mask	0x00000000,0
	.fmask	0x00000000,0
	.set	noreorder
	.set	nomacro
	
	sll	$12,$5,1
	subu	$12,$0,$12
	addu	$13,$12,$4
	addu	$14,$4,$5
	lbu	$8,0($13)
	lbu	$10,0($14)
	subu	$11,$4,$5
	lbu	$6,0($11)
	lbu	$7,0($4)
	subu	$3,$8,$10
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,3
	addiu	$3,$3,4
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$10,$3,$10
	subu	$8,$8,$3
	subu	$6,$6,$2
	addiu	$9,$4,1
	sb	$8,0($13)
	addu	$15,$5,$9
	sb	$6,0($11)
	addu	$13,$12,$9
	sb	$7,0($4)
	sb	$10,0($14)
	lbu	$8,0($13)
	lbu	$11,0($15)
	subu	$9,$9,$5
	lbu	$6,0($9)
	lbu	$7,1($4)
	subu	$3,$8,$11
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,4
	addiu	$3,$3,3
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$11,$3,$11
	subu	$8,$8,$3
	subu	$6,$6,$2
	addiu	$10,$4,2
	sb	$8,0($13)
	addu	$14,$5,$10
	sb	$6,0($9)
	addu	$13,$12,$10
	sb	$7,1($4)
	sb	$11,0($15)
	lbu	$8,0($13)
	lbu	$11,0($14)
	subu	$10,$10,$5
	lbu	$6,0($10)
	lbu	$7,2($4)
	subu	$3,$8,$11
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,3
	addiu	$3,$3,4
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$11,$3,$11
	subu	$8,$8,$3
	subu	$6,$6,$2
	addiu	$9,$4,3
	sb	$8,0($13)
	addu	$15,$5,$9
	sb	$6,0($10)
	addu	$13,$12,$9
	sb	$7,2($4)
	sb	$11,0($14)
	lbu	$8,0($13)
	lbu	$11,0($15)
	subu	$9,$9,$5
	lbu	$6,0($9)
	lbu	$7,3($4)
	subu	$3,$8,$11
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,4
	addiu	$3,$3,3
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$11,$3,$11
	subu	$8,$8,$3
	subu	$6,$6,$2
	addiu	$10,$4,4
	sb	$8,0($13)
	addu	$14,$5,$10
	sb	$6,0($9)
	addu	$13,$12,$10
	sb	$7,3($4)
	sb	$11,0($15)
	lbu	$8,0($13)
	lbu	$11,0($14)
	subu	$10,$10,$5
	lbu	$6,0($10)
	subu	$3,$8,$11
	lbu	$7,4($4)
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,3
	addiu	$3,$3,4
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$11,$3,$11
	subu	$8,$8,$3
	subu	$6,$6,$2
	addiu	$9,$4,5
	sb	$8,0($13)
	addu	$15,$5,$9
	sb	$6,0($10)
	addu	$13,$12,$9
	sb	$7,4($4)
	sb	$11,0($14)
	lbu	$8,0($13)
	lbu	$11,0($15)
	subu	$9,$9,$5
	lbu	$6,0($9)
	lbu	$7,5($4)
	subu	$3,$8,$11
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,4
	addiu	$3,$3,3
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$11,$3,$11
	subu	$8,$8,$3
	subu	$6,$6,$2
	addiu	$10,$4,6
	sb	$8,0($13)
	addu	$14,$5,$10
	sb	$6,0($9)
	addu	$13,$12,$10
	sb	$7,5($4)
	sb	$11,0($15)
	lbu	$9,0($13)
	lbu	$11,0($14)
	subu	$10,$10,$5
	lbu	$6,0($10)
	lbu	$7,6($4)
	subu	$3,$9,$11
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,3
	addiu	$3,$3,4
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	subu	$9,$9,$3
	subu	$6,$6,$2
	addiu	$8,$4,7
	addu	$11,$3,$11
	sb	$9,0($13)
	addu	$12,$12,$8
	sb	$6,0($10)
	addu	$13,$5,$8
	sb	$7,6($4)
	sb	$11,0($14)
	lbu	$7,0($12)
	lbu	$9,0($13)
	subu	$8,$8,$5
	lbu	$5,0($8)
	lbu	$6,7($4)
	subu	$3,$7,$9
	addu	$2,$5,$3
	subu	$2,$2,$6
	addiu	$2,$2,4
	addiu	$3,$3,3
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$6,$2,$6
	addu	$9,$3,$9
	subu	$7,$7,$3
	subu	$5,$5,$2
	sb	$7,0($12)
	sb	$5,0($8)
	sb	$6,7($4)
	j	$31
	sb	$9,0($13)

	.set	macro
	.set	reorder
	.end	vc1_v_overlap_c
	.section	.text.vc1_h_overlap_c,"ax",@progbits
	.align	2
	.align	5
	.ent	vc1_h_overlap_c
	.type	vc1_h_overlap_c, @function
vc1_h_overlap_c:
	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
	.mask	0x00000000,0
	.fmask	0x00000000,0
	.set	noreorder
	.set	nomacro
	
	lbu	$8,-2($4)
	lbu	$9,1($4)
	lbu	$6,-1($4)
	lbu	$7,0($4)
	subu	$3,$8,$9
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,3
	addiu	$3,$3,4
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$9,$3,$9
	subu	$8,$8,$3
	subu	$6,$6,$2
	sb	$8,-2($4)
	sb	$6,-1($4)
	sb	$7,0($4)
	sb	$9,1($4)
	addu	$4,$5,$4
	lbu	$8,-2($4)
	lbu	$9,1($4)
	lbu	$6,-1($4)
	lbu	$7,0($4)
	subu	$3,$8,$9
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,4
	addiu	$3,$3,3
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$9,$3,$9
	subu	$8,$8,$3
	subu	$6,$6,$2
	sb	$8,-2($4)
	sb	$6,-1($4)
	sb	$7,0($4)
	sb	$9,1($4)
	addu	$4,$5,$4
	lbu	$8,-2($4)
	lbu	$9,1($4)
	lbu	$6,-1($4)
	lbu	$7,0($4)
	subu	$3,$8,$9
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,3
	addiu	$3,$3,4
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$9,$3,$9
	subu	$8,$8,$3
	subu	$6,$6,$2
	sb	$8,-2($4)
	sb	$6,-1($4)
	sb	$7,0($4)
	sb	$9,1($4)
	addu	$4,$5,$4
	lbu	$8,-2($4)
	lbu	$9,1($4)
	lbu	$6,-1($4)
	lbu	$7,0($4)
	subu	$3,$8,$9
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,4
	addiu	$3,$3,3
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$9,$3,$9
	subu	$8,$8,$3
	subu	$6,$6,$2
	sb	$8,-2($4)
	sb	$6,-1($4)
	sb	$7,0($4)
	sb	$9,1($4)
	addu	$4,$5,$4
	lbu	$8,-2($4)
	lbu	$9,1($4)
	lbu	$6,-1($4)
	lbu	$7,0($4)
	subu	$3,$8,$9
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,3
	addiu	$3,$3,4
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$9,$3,$9
	subu	$8,$8,$3
	subu	$6,$6,$2
	sb	$8,-2($4)
	sb	$6,-1($4)
	sb	$7,0($4)
	sb	$9,1($4)
	addu	$4,$5,$4
	lbu	$8,-2($4)
	lbu	$9,1($4)
	lbu	$6,-1($4)
	lbu	$7,0($4)
	subu	$3,$8,$9
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,4
	addiu	$3,$3,3
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$9,$3,$9
	subu	$8,$8,$3
	subu	$6,$6,$2
	sb	$8,-2($4)
	sb	$6,-1($4)
	sb	$7,0($4)
	sb	$9,1($4)
	addu	$4,$5,$4
	lbu	$8,-2($4)
	lbu	$9,1($4)
	lbu	$6,-1($4)
	lbu	$7,0($4)
	subu	$3,$8,$9
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,3
	addiu	$3,$3,4
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	subu	$8,$8,$3
	subu	$6,$6,$2
	addu	$9,$3,$9
	sb	$8,-2($4)
	sb	$6,-1($4)
	sb	$7,0($4)
	sb	$9,1($4)
	addu	$5,$5,$4
	lbu	$8,-2($5)
	lbu	$4,1($5)
	lbu	$6,-1($5)
	subu	$3,$8,$4
	lbu	$7,0($5)
	addu	$2,$6,$3
	subu	$2,$2,$7
	addiu	$2,$2,4
	addiu	$3,$3,3
	sra	$3,$3,3
	sra	$2,$2,3
	andi	$3,$3,0x00ff
	andi	$2,$2,0x00ff
	addu	$7,$2,$7
	addu	$4,$3,$4
	subu	$8,$8,$3
	subu	$6,$6,$2
	sb	$4,1($5)
	sb	$8,-2($5)
	sb	$6,-1($5)
	j	$31
	sb	$7,0($5)

	.set	macro
	.set	reorder
	.end	vc1_h_overlap_c
	.section	.text.vc1_inv_trans_8x8_c,"ax",@progbits
	.align	2
	.align	5
	.ent	vc1_inv_trans_8x8_c
	.type	vc1_inv_trans_8x8_c, @function
vc1_inv_trans_8x8_c:
	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
	.mask	0x00000000,0
	.fmask	0x00000000,0
	li	$2,786432			# 0xc0000
	ori	$2,$2,0xc
#APP
	S32I2M xr15,$2
#NO_APP
	li	$3,1048576			# 0x100000
	ori	$3,$3,0x6
#APP
	S32I2M xr14,$3
#NO_APP
	li	$2,1048576			# 0x100000
	ori	$2,$2,0xf
#APP
	S32I2M xr13,$2
#NO_APP
	li	$3,589824			# 0x90000
	ori	$3,$3,0x4
#APP
	S32I2M xr12,$3
	S32LDD xr1,$4,0
	S32LDD xr2,$4,4
	S32LDD xr3,$4,8
	S32LDD xr4,$4,12
	D16MUL xr5,xr1,xr15,xr6,LW
	D16MAC xr5,xr3,xr15,xr6,AS,LW
	D16MUL xr7,xr2,xr14,xr8,LW
	D16MAC xr8,xr4,xr14,xr7,SA,LW
	D32ADD xr5,xr5,xr7,xr7,AS
	D32ADD xr6,xr6,xr8,xr8,AS
#NO_APP
	li	$2,4			# 0x4
#APP
	S32I2M xr9,$2
	D32ACC xr5,xr9,xr0,xr7,AS
	D32ACC xr6,xr9,xr0,xr8,AS
	D16MUL xr9,xr1,xr13,xr10,HW
	D16MUL xr11,xr1,xr12,xr1,HW
	D16MAC xr11,xr2,xr13,xr9,SA,HW
	D16MAC xr1,xr2,xr12,xr10,SS,HW
	D16MAC xr10,xr3,xr13,xr1,SA,HW
	D16MAC xr9,xr3,xr12,xr11,AA,HW
	D16MAC xr1,xr4,xr13,xr11,SA,HW
	D16MAC xr10,xr4,xr12,xr9,SA,HW
	D32ADD xr5,xr5,xr9,xr9,AS
	D32ADD xr6,xr6,xr10,xr10,AS
	D32ADD xr8,xr8,xr11,xr11,AS
	D32ADD xr7,xr7,xr1,xr1,AS
	D32SARL xr5,xr6,xr5,3
	D32SARL xr6,xr7,xr8,3
	D32SARL xr7,xr11,xr1,3
	D32SARL xr8,xr9,xr10,3
	S32STD xr5,$4,0
	S32STD xr6,$4,4
	S32STD xr7,$4,8
	S32STD xr8,$4,12
#NO_APP
	addiu	$2,$4,16
#APP
	S32LDD xr1,$2,0
	S32LDD xr2,$2,4
	S32LDD xr3,$2,8
	S32LDD xr4,$2,12
	D16MUL xr5,xr1,xr15,xr6,LW
	D16MAC xr5,xr3,xr15,xr6,AS,LW
	D16MUL xr7,xr2,xr14,xr8,LW
	D16MAC xr8,xr4,xr14,xr7,SA,LW
	D32ADD xr5,xr5,xr7,xr7,AS
	D32ADD xr6,xr6,xr8,xr8,AS
#NO_APP
	li	$3,4			# 0x4
#APP
	S32I2M xr9,$3
	D32ACC xr5,xr9,xr0,xr7,AS
	D32ACC xr6,xr9,xr0,xr8,AS
	D16MUL xr9,xr1,xr13,xr10,HW
	D16MUL xr11,xr1,xr12,xr1,HW
	D16MAC xr11,xr2,xr13,xr9,SA,HW
	D16MAC xr1,xr2,xr12,xr10,SS,HW
	D16MAC xr10,xr3,xr13,xr1,SA,HW
	D16MAC xr9,xr3,xr12,xr11,AA,HW
	D16MAC xr1,xr4,xr13,xr11,SA,HW
	D16MAC xr10,xr4,xr12,xr9,SA,HW
	D32ADD xr5,xr5,xr9,xr9,AS
	D32ADD xr6,xr6,xr10,xr10,AS
	D32ADD xr8,xr8,xr11,xr11,AS
	D32ADD xr7,xr7,xr1,xr1,AS
	D32SARL xr5,xr6,xr5,3
	D32SARL xr6,xr7,xr8,3
	D32SARL xr7,xr11,xr1,3
	D32SARL xr8,xr9,xr10,3
	S32STD xr5,$2,0
	S32STD xr6,$2,4
	S32STD xr7,$2,8
	S32STD xr8,$2,12
#NO_APP
	addiu	$2,$2,16
#APP
	S32LDD xr1,$2,0
	S32LDD xr2,$2,4
	S32LDD xr3,$2,8
	S32LDD xr4,$2,12
	D16MUL xr5,xr1,xr15,xr6,LW
	D16MAC xr5,xr3,xr15,xr6,AS,LW
	D16MUL xr7,xr2,xr14,xr8,LW
	D16MAC xr8,xr4,xr14,xr7,SA,LW
	D32ADD xr5,xr5,xr7,xr7,AS
	D32ADD xr6,xr6,xr8,xr8,AS
	S32I2M xr9,$3
	D32ACC xr5,xr9,xr0,xr7,AS
	D32ACC xr6,xr9,xr0,xr8,AS
	D16MUL xr9,xr1,xr13,xr10,HW
	D16MUL xr11,xr1,xr12,xr1,HW
	D16MAC xr11,xr2,xr13,xr9,SA,HW
	D16MAC xr1,xr2,xr12,xr10,SS,HW
	D16MAC xr10,xr3,xr13,xr1,SA,HW
	D16MAC xr9,xr3,xr12,xr11,AA,HW
	D16MAC xr1,xr4,xr13,xr11,SA,HW
	D16MAC xr10,xr4,xr12,xr9,SA,HW
	D32ADD xr5,xr5,xr9,xr9,AS
	D32ADD xr6,xr6,xr10,xr10,AS
	D32ADD xr8,xr8,xr11,xr11,AS
	D32ADD xr7,xr7,xr1,xr1,AS
	D32SARL xr5,xr6,xr5,3
	D32SARL xr6,xr7,xr8,3
	D32SARL xr7,xr11,xr1,3
	D32SARL xr8,xr9,xr10,3
	S32STD xr5,$2,0
	S32STD xr6,$2,4
	S32STD xr7,$2,8
	S32STD xr8,$2,12
#NO_APP
	addiu	$2,$2,16
#APP
	S32LDD xr1,$2,0
	S32LDD xr2,$2,4
	S32LDD xr3,$2,8
	S32LDD xr4,$2,12
	D16MUL xr5,xr1,xr15,xr6,LW
	D16MAC xr5,xr3,xr15,xr6,AS,LW
	D16MUL xr7,xr2,xr14,xr8,LW
	D16MAC xr8,xr4,xr14,xr7,SA,LW
	D32ADD xr5,xr5,xr7,xr7,AS
	D32ADD xr6,xr6,xr8,xr8,AS
	S32I2M xr9,$3
	D32ACC xr5,xr9,xr0,xr7,AS
	D32ACC xr6,xr9,xr0,xr8,AS
	D16MUL xr9,xr1,xr13,xr10,HW
	D16MUL xr11,xr1,xr12,xr1,HW
	D16MAC xr11,xr2,xr13,xr9,SA,HW
	D16MAC xr1,xr2,xr12,xr10,SS,HW
	D16MAC xr10,xr3,xr13,xr1,SA,HW
	D16MAC xr9,xr3,xr12,xr11,AA,HW
	D16MAC xr1,xr4,xr13,xr11,SA,HW
	D16MAC xr10,xr4,xr12,xr9,SA,HW
	D32ADD xr5,xr5,xr9,xr9,AS
	D32ADD xr6,xr6,xr10,xr10,AS
	D32ADD xr8,xr8,xr11,xr11,AS
	D32ADD xr7,xr7,xr1,xr1,AS
	D32SARL xr5,xr6,xr5,3
	D32SARL xr6,xr7,xr8,3
	D32SARL xr7,xr11,xr1,3
	D32SARL xr8,xr9,xr10,3
	S32STD xr5,$2,0
	S32STD xr6,$2,4
	S32STD xr7,$2,8
	S32STD xr8,$2,12
#NO_APP
	addiu	$2,$2,16
#APP
	S32LDD xr1,$2,0
	S32LDD xr2,$2,4
	S32LDD xr3,$2,8
	S32LDD xr4,$2,12
	D16MUL xr5,xr1,xr15,xr6,LW
	D16MAC xr5,xr3,xr15,xr6,AS,LW
	D16MUL xr7,xr2,xr14,xr8,LW
	D16MAC xr8,xr4,xr14,xr7,SA,LW
	D32ADD xr5,xr5,xr7,xr7,AS
	D32ADD xr6,xr6,xr8,xr8,AS
	S32I2M xr9,$3
	D32ACC xr5,xr9,xr0,xr7,AS
	D32ACC xr6,xr9,xr0,xr8,AS
	D16MUL xr9,xr1,xr13,xr10,HW
	D16MUL xr11,xr1,xr12,xr1,HW
	D16MAC xr11,xr2,xr13,xr9,SA,HW