savage_vid.c

来自「君正早期ucos系统(只有早期的才不没有打包成库),MPLAYER,文件系统,图」· C语言 代码 · 共 1,412 行 · 第 1/3 页

/*
 * VIDIX driver for S3 Savage chipsets.
 * Copyright (C) 2004 Reza Jelveh
 *
 * This file is part of MPlayer.
 *
 * MPlayer is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * MPlayer is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with MPlayer; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 *
 * Thanks to Alex Deucher for Support
 */

#include <errno.h>
#include <mplaylib.h>
#include <mplaylib.h>
#include <mplaylib.h>
#include <inttypes.h>
#include <mplaylib.h>
#include <math.h>

#include "vidix.h"
#include "vidixlib.h"
#include "fourcc.h"
#include "dha.h"
#include "pci_ids.h"
#include "pci_names.h"
#include "config.h"

#include "savage_regs.h"

#undef memcpy
#define memcpy uc_memcpy
#define VF_STREAMS_ON   0x0001
#define BASE_PAD 0xf
#define FRAMEBUFFER_SIZE 1024*2000*4
/**************************************
   S3 streams processor
**************************************/

#define EXT_MISC_CTRL2              0x67

/* New streams */

/* CR67[2] = 1 : enable stream 1 */
#define ENABLE_STREAM1              0x04
/* CR67[1] = 1 : enable stream 2 */
#define ENABLE_STREAM2              0x02
/* mask to clear CR67[2,1] */
#define NO_STREAMS                  0xF9
/* CR67[3] = 1 : Mem-mapped regs */
#define USE_MM_FOR_PRI_STREAM       0x08

#define HDM_SHIFT	16
#define HDSCALE_4	(2 << HDM_SHIFT)
#define HDSCALE_8	(3 << HDM_SHIFT)
#define HDSCALE_16	(4 << HDM_SHIFT)
#define HDSCALE_32	(5 << HDM_SHIFT)
#define HDSCALE_64	(6 << HDM_SHIFT)

/* Old Streams */

#define ENABLE_STREAMS_OLD	    0x0c
#define NO_STREAMS_OLD		    0xf3
/* CR69[0] = 1 : Mem-mapped regs */
#define USE_MM_FOR_PRI_STREAM_OLD   0x01

static void SavageStreamsOn(void);

/*
 * There are two different streams engines used in the Savage line.
 * The old engine is in the 3D, 4, Pro, and Twister.
 * The new engine is in the 2000, MX, IX, and Super.
 */


/* streams registers for old engine */
#define PSTREAM_CONTROL_REG		0x8180
#define COL_CHROMA_KEY_CONTROL_REG	0x8184
#define SSTREAM_CONTROL_REG		0x8190
#define CHROMA_KEY_UPPER_BOUND_REG	0x8194
#define SSTREAM_STRETCH_REG		0x8198
#define COLOR_ADJUSTMENT_REG		0x819C
#define BLEND_CONTROL_REG		0x81A0
#define PSTREAM_FBADDR0_REG		0x81C0
#define PSTREAM_FBADDR1_REG		0x81C4
#define PSTREAM_STRIDE_REG		0x81C8
#define DOUBLE_BUFFER_REG		0x81CC
#define SSTREAM_FBADDR0_REG		0x81D0
#define SSTREAM_FBADDR1_REG		0x81D4
#define SSTREAM_STRIDE_REG		0x81D8
#define SSTREAM_VSCALE_REG		0x81E0
#define SSTREAM_VINITIAL_REG		0x81E4
#define SSTREAM_LINES_REG		0x81E8
#define STREAMS_FIFO_REG		0x81EC
#define PSTREAM_WINDOW_START_REG	0x81F0
#define PSTREAM_WINDOW_SIZE_REG		0x81F4
#define SSTREAM_WINDOW_START_REG	0x81F8
#define SSTREAM_WINDOW_SIZE_REG		0x81FC
#define FIFO_CONTROL			0x8200
#define PSTREAM_FBSIZE_REG		0x8300
#define SSTREAM_FBSIZE_REG		0x8304
#define SSTREAM_FBADDR2_REG		0x8308

#define OS_XY(x,y)	(((x+1)<<16)|(y+1))
#define OS_WH(x,y)	(((x-1)<<16)|(y))

#define PCI_COMMAND_MEM 0x2
#define MAX_FRAMES 3
/**
 * @brief Information on PCI device.
 */
static pciinfo_t pci_info;

#define outb(reg,val)	OUTPORT8(reg,val)
#define inb(reg)	INPORT8(reg)
#define outw(reg,val)	OUTPORT16(reg,val)
#define inw(reg)	INPORT16(reg)
#define outl(reg,val)	OUTPORT32(reg,val)
#define inl(reg)	INPORT32(reg)


/*
 * PCI-Memory IO access macros.
 */
#define VID_WR08(p,i,val)  (((uint8_t *)(p))[(i)]=(val))
#define VID_RD08(p,i)	   (((uint8_t *)(p))[(i)])

#define VID_WR32(p,i,val)  (((uint32_t *)(p))[(i)/4]=(val))
#define VID_RD32(p,i)	   (((uint32_t *)(p))[(i)/4])

#ifndef USE_RMW_CYCLES
/*
 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default.
 */

#define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory")

#undef	VID_WR08
#define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); })
#undef	VID_RD08
#define VID_RD08(p,i)     ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; })

#undef	VID_WR16
#define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); })
#undef	VID_RD16
#define VID_RD16(p,i)     ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; })

#undef	VID_WR32
#define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); })
#undef	VID_RD32
#define VID_RD32(p,i)     ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; })
#endif /* USE_RMW_CYCLES */

#define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val))
#define VID_OR32(p,i,val)  VID_WR32(p,i,VID_RD32(p,i)|(val))
#define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val))


/* from x driver */

#define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr)
#define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr)
#define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr)

#define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val)
#define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val)
#define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val)

#define INREG(addr) VID_RD32(info->control_base, addr)
#define OUTREG(addr,val) VID_WR32(info->control_base, addr, val)
#define INREG8(addr) VID_RD08(info->control_base, addr)
#define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val)
#define INREG16(addr) VID_RD16(info->control_base, addr)
#define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val)

#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1))


static void debugout(unsigned int addr, unsigned int val);


struct savage_chip {
	volatile uint32_t *PMC;	   /* general control			*/
	volatile uint32_t *PME;	   /* multimedia port			*/
	volatile uint32_t *PFB;	   /* framebuffer control		*/
	volatile uint32_t *PVIDEO; /* overlay control			*/
	volatile uint8_t  *PCIO;   /* SVGA (CRTC, ATTR) registers	*/
	volatile uint8_t  *PVIO;   /* SVGA (MISC, GRAPH, SEQ) registers */
	volatile uint32_t *PRAMIN; /* instance memory			*/
	volatile uint32_t *PRAMHT; /* hash table			*/
	volatile uint32_t *PRAMFC; /* fifo context table		*/
	volatile uint32_t *PRAMRO; /* fifo runout table			*/
	volatile uint32_t *PFIFO;  /* fifo control region		*/
	volatile uint32_t *FIFO;   /* fifo channels (USER)		*/
	volatile uint32_t *PGRAPH; /* graphics engine                   */

	int arch;		   /* compatible NV_ARCH_XX define */
	unsigned long fbsize;		   /* framebuffer size		   */
	void (* lock) (struct savage_chip *, int);
};
typedef struct savage_chip savage_chip;


struct savage_info {
    unsigned int use_colorkey;    
    unsigned int colorkey; /* saved xv colorkey*/
    unsigned int vidixcolorkey; /*currently used colorkey*/
    unsigned int depth; 
    unsigned int bpp; 
    unsigned int videoFlags;
    unsigned int format;
    unsigned int pitch;
    unsigned int blendBase;
    unsigned int lastKnownPitch;
    unsigned int displayWidth, displayHeight;
    unsigned int brightness,hue,saturation,contrast;
    unsigned int src_w,src_h;
    unsigned int drw_w,drw_h;  /*scaled width && height*/
    unsigned int wx,wy;                /*window x && y*/
    unsigned int screen_x;            /*screen width*/
    unsigned int screen_y;            /*screen height*/
    unsigned long buffer_size;		 /* size of the image buffer	       */
    struct savage_chip chip;	 /* NV architecture structure		       */
    void* video_base;		 /* virtual address of control region	       */
    void* control_base;		 /* virtual address of fb region	       */
    unsigned long picture_base;	 /* direct pointer to video picture	       */
    unsigned long picture_offset;	 /* offset of video picture in frame buffer    */
//	struct savage_dma dma;           /* DMA structure                              */
    unsigned int cur_frame;
    unsigned int num_frames;             /* number of buffers                          */
    int bps;			/* bytes per line */
  void (*SavageWaitIdle) ();
  void (*SavageWaitFifo) (int space);
};
typedef struct savage_info savage_info;


static savage_info* info;


/**
 * @brief Unichrome driver vidix capabilities.
 */
static vidix_capability_t savage_cap = {
  "Savage/ProSavage/Twister vidix",
  "Reza Jelveh <[e-mail]>",
  TYPE_OUTPUT,
  {0, 0, 0, 0},
  4096,
  4096,
  4,
  4,
  -1,
  FLAG_UPSCALER | FLAG_DOWNSCALER,
  VENDOR_S3_INC,
  -1,
  {0, 0, 0, 0}
};

struct savage_cards {
  unsigned short chip_id;
  unsigned short arch;
};


static
unsigned int GetBlendForFourCC( int id )
{
    switch( id ) {
	case IMGFMT_YUY2:
	case IMGFMT_YV12:
	case IMGFMT_I420:
	    return 1;
	case IMGFMT_Y211:
	    return 4;
	case IMGFMT_RGB15:
	    return 3;
	case IMGFMT_RGB16:
	    return 5;
        default:
	    return 0;
    }
}

/**
 * @brief list of card IDs compliant with the Unichrome driver .
 */
static struct savage_cards savage_card_ids[] = {
	/*[ProSavage PN133] AGP4X VGA Controller (Twister)*/
	{ PCI_CHIP_S3TWISTER_P, 	       		S3_PROSAVAGE },
	/*[ProSavage KN133] AGP4X VGA Controller (TwisterK)*/
	{ PCI_CHIP_S3TWISTER_K, 	       		S3_PROSAVAGE },
	/*ProSavage DDR*/
	{ PCI_CHIP_PROSAVAGE_DDR	, 		       		S3_PROSAVAGE },
	/*[ProSavageDDR P4M266 K] */
	{ PCI_CHIP_PROSAVAGE_DDRK	, 			S3_PROSAVAGE },
};

static void SavageSetColorOld(void)
{


  if( 
  (info->format == IMGFMT_RGB15) ||
	(info->format == IMGFMT_RGB16)
    )
    {
  OUTREG( COLOR_ADJUSTMENT_REG, 0 );
    }
    else
    {
        /* Change 0..255 into 0..15 */
  long sat = info->saturation * 16 / 256;
  double hue = info->hue * 0.017453292;
  unsigned long hs1 = ((long)(sat * cos(hue))) & 0x1f;
  unsigned long hs2 = ((long)(sat * sin(hue))) & 0x1f;

  OUTREG( COLOR_ADJUSTMENT_REG, 
      0x80008000 |
      (info->brightness + 128) |
      ((info->contrast & 0xf8) << (12-7)) | 
      (hs1 << 16) |
      (hs2 << 24)
  );
  debugout( COLOR_ADJUSTMENT_REG, 
      0x80008000 |
      (info->brightness + 128) |
      ((info->contrast & 0xf8) << (12-7)) | 
      (hs1 << 16) |
      (hs2 << 24)
  );
  
  }
}

static void SavageSetColorKeyOld(void)
{
    int red, green, blue;

    /* Here, we reset the colorkey and all the controls. */

    red = (info->vidixcolorkey & 0x00FF0000) >> 16;
    green = (info->vidixcolorkey & 0x0000FF00) >> 8;
    blue = info->vidixcolorkey & 0x000000FF;

    if( !info->vidixcolorkey ) {
      printf("SavageSetColorKey disabling colorkey\n");
      OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 );
      OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 );
      OUTREG( BLEND_CONTROL_REG, 0 );
    }
    else {
	switch (info->depth) {
		// FIXME: isnt fixed yet
	case 8:
	    OUTREG( COL_CHROMA_KEY_CONTROL_REG,
		0x37000000 | (info->vidixcolorkey & 0xFF) );
	    OUTREG( CHROMA_KEY_UPPER_BOUND_REG,
		0x00000000 | (info->vidixcolorkey & 0xFF) );
	    break;
	case 15:
			/* 15 bpp 555 */
      red&=0x1f;
      green&=0x1f;
      blue&=0x1f;
	    OUTREG( COL_CHROMA_KEY_CONTROL_REG, 
		0x05000000 | (red<<19) | (green<<11) | (blue<<3) );
	    OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 
		0x00000000 | (red<<19) | (green<<11) | (blue<<3) );
	    break;
	case 16:
			/* 16 bpp 565 */
      red&=0x1f;
      green&=0x3f;
      blue&=0x1f;
	    OUTREG( COL_CHROMA_KEY_CONTROL_REG, 
		0x16000000 | (red<<19) | (green<<10) | (blue<<3) );
	    OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 
		0x00020002 | (red<<19) | (green<<10) | (blue<<3) );
	    break;
	case 24:
			/* 24 bpp 888 */
	    OUTREG( COL_CHROMA_KEY_CONTROL_REG, 
		0x17000000 | (red<<16) | (green<<8) | (blue) );
	    OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 
		0x00000000 | (red<<16) | (green<<8) | (blue) );
	    break;
	}    

	/* We use destination colorkey */
	OUTREG( BLEND_CONTROL_REG, 0x05000000 );
  }
}


static void
SavageDisplayVideoOld(void)
{
    int vgaCRIndex, vgaCRReg, vgaIOBase;
    unsigned int ssControl;
    int cr92;


    vgaIOBase = 0x3d0;
    vgaCRIndex = vgaIOBase + 4;
    vgaCRReg = vgaIOBase + 5;

//    if( psav->videoFourCC != id )
//	SavageStreamsOff(pScrn);

    if( !info->videoFlags & VF_STREAMS_ON )
    {
				SavageStreamsOn();
	//	SavageResetVideo();
        SavageSetColorOld();
				SavageSetColorKeyOld();
    }
   



    /* Set surface format. */

		OUTREG(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w);

		debugout(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w);

    /* Calculate horizontal scale factor. */

    //FIXME: enable scaling
    OUTREG(SSTREAM_STRETCH_REG, (info->src_w << 15) / info->drw_w );
//    debugout(SSTREAM_STRETCH_REG, 1 << 15);

    OUTREG(SSTREAM_LINES_REG, info->src_h );
    debugout(SSTREAM_LINES_REG, info->src_h );


    OUTREG(SSTREAM_VINITIAL_REG, 0 );
    debugout(SSTREAM_VINITIAL_REG, 0 );
    /* Calculate vertical scale factor. */

//    OUTREG(SSTREAM_VSCALE_REG, 1 << 15);
    OUTREG(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) );
    debugout(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) );
//    OUTREG(SSTREAM_VSCALE_REG, (info->src_h << 15) / info->drw_h );

    /* Set surface location and stride. */

    OUTREG(SSTREAM_FBADDR0_REG, info->picture_offset  );
    debugout(SSTREAM_FBADDR0_REG, info->picture_offset  );

    OUTREG(SSTREAM_FBADDR1_REG, 0 );
    debugout(SSTREAM_FBADDR1_REG, 0 );
    
    OUTREG(SSTREAM_STRIDE_REG, info->pitch );
    debugout(SSTREAM_STRIDE_REG, info->pitch );

    OUTREG(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) );
    debugout(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) );
    OUTREG(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) );