radeon_vid.c

来自「君正早期ucos系统(只有早期的才不没有打包成库),MPLAYER,文件系统,图」· C语言 代码 · 共 2,049 行 · 第 1/5 页

 { DEVICE_ATI_RV280_RADEON_92006,	R_280 },
 { DEVICE_ATI_RV280_RADEON_92007,	R_280 },
 { DEVICE_ATI_M9_5C61_RADEON,		R_280 },
 { DEVICE_ATI_M9_5C63_RADEON,		R_280 },
/* Radeon3 (indeed: Rage 1024 Pro ;) */
 { DEVICE_ATI_R300_AG_FIREGL,		R_300 },
 { DEVICE_ATI_RADEON_R300_ND,		R_300 },
 { DEVICE_ATI_RADEON_R300_NE,		R_300 },
 { DEVICE_ATI_RADEON_R300_NG,		R_300 },
 { DEVICE_ATI_R300_AD_RADEON,		R_300 },
 { DEVICE_ATI_R300_AE_RADEON,		R_300 },
 { DEVICE_ATI_R300_AF_RADEON,		R_300 },
 { DEVICE_ATI_RADEON_9100_IGP2,		R_300|R_OVL_SHIFT|R_INTEGRATED },
 { DEVICE_ATI_RS300M_AGP_RADEON,	R_300|R_INTEGRATED },
 { DEVICE_ATI_RS482_RADEON_XPRESS,	R_350|R_INTEGRATED },
 { DEVICE_ATI_R350_AH_RADEON,		R_350 },
 { DEVICE_ATI_R350_AI_RADEON,		R_350 },
 { DEVICE_ATI_R350_AJ_RADEON,		R_350 },
 { DEVICE_ATI_R350_AK_FIRE,		R_350 },
 { DEVICE_ATI_RADEON_R350_RADEON2,	R_350 },
 { DEVICE_ATI_RADEON_R350_RADEON3,	R_350 },
 { DEVICE_ATI_RV350_NJ_RADEON,		R_350 },
 { DEVICE_ATI_R350_NK_FIRE,		R_350 },
 { DEVICE_ATI_RV350_AP_RADEON,		R_350 },
 { DEVICE_ATI_RV350_AQ_RADEON,		R_350 },
 { DEVICE_ATI_RV350_AR_RADEON,		R_350 },
 { DEVICE_ATI_RV350_AS_RADEON,		R_350 },
 { DEVICE_ATI_RV350_AT_FIRE,		R_350 },
 { DEVICE_ATI_RV350_AU_FIRE,		R_350 },
 { DEVICE_ATI_RV350_AV_FIRE,		R_350 },
 { DEVICE_ATI_RV350_AW_FIRE,		R_350 },
 { DEVICE_ATI_RV350_MOBILITY_RADEON,	R_350 },
 { DEVICE_ATI_RV350_NF_RADEON,		R_300 },
 { DEVICE_ATI_RV350_NJ_RADEON,		R_300 },
 { DEVICE_ATI_RV350_AS_RADEON2,		R_350 },
 { DEVICE_ATI_M10_NQ_RADEON,		R_350 },
 { DEVICE_ATI_M10_NQ_RADEON2,		R_350 },
 { DEVICE_ATI_RV350_MOBILITY_RADEON2,	R_350 },
 { DEVICE_ATI_M10_NS_RADEON,		R_350 },
 { DEVICE_ATI_M10_NT_FIREGL,		R_350 },
 { DEVICE_ATI_M11_NV_FIREGL,		R_350 },
 { DEVICE_ATI_RV370_5B60_RADEON,	R_370|R_PCIE  },
 { DEVICE_ATI_RV370_SAPPHIRE_X550,	R_370 },
 { DEVICE_ATI_RV370_5B64_FIREGL,	R_370|R_PCIE  },
 { DEVICE_ATI_RV370_5B65_FIREGL,	R_370|R_PCIE  },
 { DEVICE_ATI_M24_1P_RADEON,		R_370  },
 { DEVICE_ATI_M22_RADEON_MOBILITY,	R_370  },
 { DEVICE_ATI_M24_1T_FIREGL,		R_370  },
 { DEVICE_ATI_M24_RADEON_MOBILITY,	R_370  },
 { DEVICE_ATI_RV370_RADEON_X300SE,	R_370  },
 { DEVICE_ATI_RV370_SECONDARY_SAPPHIRE,	R_370  },
 { DEVICE_ATI_RV370_5B64_FIREGL2,	R_370  },
 { DEVICE_ATI_RV380_0X3E50_RADEON,	R_380|R_PCIE  },
 { DEVICE_ATI_RV380_0X3E54_FIREGL,	R_380|R_PCIE  },
 { DEVICE_ATI_RV380_RADEON_X600,	R_380|R_PCIE  },
 { DEVICE_ATI_RV380_RADEON_X6002,	R_380  },
 { DEVICE_ATI_RV380_RADEON_X6003,	R_380  },
 { DEVICE_ATI_RV410_FIREGL_V5000,	R_420  },
 { DEVICE_ATI_RV410_FIREGL_V3300,	R_420  },
 { DEVICE_ATI_RV410_RADEON_X700XT,	R_420  },
 { DEVICE_ATI_RV410_RADEON_X700,	R_420|R_PCIE  },
 { DEVICE_ATI_RV410_RADEON_X700SE,	R_420  },
 { DEVICE_ATI_RV410_RADEON_X7002,	R_420|R_PCIE  },
 { DEVICE_ATI_RV410_RADEON_X7003,	R_420  },
 { DEVICE_ATI_RV410_RADEON_X7004,	R_420|R_PCIE  },
 { DEVICE_ATI_RV410_RADEON_X7005,	R_420|R_PCIE  },
 { DEVICE_ATI_M26_MOBILITY_FIREGL,	R_420  },
 { DEVICE_ATI_M26_MOBILITY_FIREGL2,	R_420  },
 { DEVICE_ATI_M26_RADEON_MOBILITY,	R_420  },
 { DEVICE_ATI_M26_RADEON_MOBILITY2,	R_420  },
 { DEVICE_ATI_RADEON_MOBILITY_X700,	R_420  },
 { DEVICE_ATI_R420_JH_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R420_JI_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R420_JJ_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R420_JK_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R420_JL_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R420_JM_FIREGL,		R_420|R_PCIE  },
 { DEVICE_ATI_M18_JN_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R420_JP_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R420_RADEON_X800,		R_420|R_PCIE  },
 { DEVICE_ATI_R420_RADEON_X8002,	R_420|R_PCIE  },
 { DEVICE_ATI_R420_RADEON_X8003,	R_420|R_PCIE  },
 { DEVICE_ATI_R420_RADEON_X8004,	R_420|R_PCIE  },
 { DEVICE_ATI_R420_RADEON_X8005,	R_420|R_PCIE  },
 { DEVICE_ATI_R420_JM_FIREGL,		R_420|R_PCIE  },
 { DEVICE_ATI_R423_5F57_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R423_5F57_RADEON2,	R_420|R_PCIE  },
 { DEVICE_ATI_R423_UH_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R423_UI_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R423_UJ_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R423_UK_RADEON,		R_420|R_PCIE  },
 { DEVICE_ATI_R423_FIRE_GL,		R_420|R_PCIE  },
 { DEVICE_ATI_R423_UQ_FIREGL,		R_420|R_PCIE  },
 { DEVICE_ATI_R423_UR_FIREGL,		R_420|R_PCIE  },
 { DEVICE_ATI_R423_UT_FIREGL,		R_420|R_PCIE  },
 { DEVICE_ATI_R423_UI_RADEON2,		R_420|R_PCIE  },
 { DEVICE_ATI_R423GL_SE_ATI_FIREGL,	R_420|R_PCIE  },
 { DEVICE_ATI_R423_RADEON_X800XT,	R_420|R_PCIE  },
 { DEVICE_ATI_RADEON_R423_UK,		R_420|R_PCIE  },
 { DEVICE_ATI_M28_RADEON_MOBILITY,	R_420  },
 { DEVICE_ATI_M28_MOBILITY_FIREGL,	R_420  },
 { DEVICE_ATI_MOBILITY_RADEON_X800,	R_420  },
 { DEVICE_ATI_R430_RADEON_X800,		R_430|R_PCIE  },
 { DEVICE_ATI_R430_RADEON_X8002,	R_430|R_PCIE  },
 { DEVICE_ATI_R430_RADEON_X8003,	R_430|R_PCIE  },
 { DEVICE_ATI_R430_RADEON_X8004,	R_430|R_PCIE  },
 { DEVICE_ATI_R480_RADEON_X800,		R_480  },
 { DEVICE_ATI_R480_RADEON_X8002,	R_480  },
 { DEVICE_ATI_R480_RADEON_X850XT,	R_480  },
 { DEVICE_ATI_R480_RADEON_X850PRO,	R_480  },
 { DEVICE_ATI_R481_RADEON_X850XT_PE,	R_480|R_PCIE  },
 { DEVICE_ATI_R480_RADEON_X850XT2,	R_480  },
 { DEVICE_ATI_R480_RADEON_X850PRO2,	R_480  },
 { DEVICE_ATI_R481_RADEON_X850XT_PE2,	R_480|R_PCIE  },
 { DEVICE_ATI_R480_RADEON_X850XT3,	R_480|R_PCIE  },
 { DEVICE_ATI_R480_RADEON_X850XT4,	R_480|R_PCIE  },
 { DEVICE_ATI_R480_RADEON_X850XT5,	R_480|R_PCIE  },
 { DEVICE_ATI_R480_RADEON_X850XT6,	R_480|R_PCIE  },
 { DEVICE_ATI_R520_FIREGL,		R_520  },
 { DEVICE_ATI_R520_GL_ATI,		R_520  },
 { DEVICE_ATI_R520_GL_ATI2,		R_520  },
 { DEVICE_ATI_R520_RADEON_X1800,	R_520  },
 { DEVICE_ATI_R520_RADEON_X18002,	R_520  },
 { DEVICE_ATI_R520_RADEON_X18003,	R_520  },
 { DEVICE_ATI_R520_RADEON_X18004,	R_520  },
 { DEVICE_ATI_R520_RADEON_X18005,	R_520  },
 { DEVICE_ATI_R520_RADEON_X18006,	R_520  },
 { DEVICE_ATI_R520_RADEON_X18007,	R_520  },
 { DEVICE_ATI_M58_RADEON_MOBILITY,	R_520  },
 { DEVICE_ATI_M58_RADEON_MOBILITY2,	R_520  },
 { DEVICE_ATI_M58_MOBILITY_FIREGL,	R_520  },
 { DEVICE_ATI_M58_MOBILITY_FIREGL2,	R_520  },
 { DEVICE_ATI_RV515_RADEON_X1600,	R_520  },
 { DEVICE_ATI_RV515_RADEON_X1300,	R_520  },
 { DEVICE_ATI_RV515_RADEON_X13002,	R_520  },
 { DEVICE_ATI_RV515_RADEON_X13003,	R_520  },
 { DEVICE_ATI_RV515_RADEON_X13004,	R_520  },
 { DEVICE_ATI_RV515_RADEON_X13005,	R_520  },
 { DEVICE_ATI_RV515_RADEON_X13006,	R_520  },
 { DEVICE_ATI_RV515_RADEON_X13007,	R_520  },
 { DEVICE_ATI_RV515_GL_ATI,		R_520  },
 { DEVICE_ATI_RV515_GL_ATI2,		R_520  },
 { DEVICE_ATI_RADEON_MOBILITY_X1400,	R_520  },
 { DEVICE_ATI_M52_ATI_MOBILITY,		R_520  },
 { DEVICE_ATI_M52_ATI_MOBILITY2,	R_520  },
 { DEVICE_ATI_M52_ATI_MOBILITY3,	R_520  },
 { DEVICE_ATI_M52_ATI_MOBILITY4,	R_520  },
 { DEVICE_ATI_RV516_RADEON_X1300,	R_520  },
 { DEVICE_ATI_RV516_RADEON_X13002,	R_520  },
 { DEVICE_ATI_RV516_XT_RADEON,		R_520  },
 { DEVICE_ATI_RV516_XT_RADEON2,		R_520  },
 { DEVICE_ATI_RV530_RADEON_X1600,	R_520  },
 { DEVICE_ATI_RV530_RADEON_X16002,	R_520  },
 { DEVICE_ATI_M56GL_ATI_MOBILITY,	R_520  },
 { DEVICE_ATI_M56P_RADEON_MOBILITY,	R_520  },
 { DEVICE_ATI_M66_P_ATI_MOBILITY,	R_520  },
 { DEVICE_ATI_M66_XT_ATI_MOBILITY,	R_520  },
 { DEVICE_ATI_RV530LE_RADEON_X1600,	R_520  },
 { DEVICE_ATI_RV530LE_RADEON_X16002,	R_520  },
 { DEVICE_ATI_RV530LE_RADEON_X16003,	R_520  },
 { DEVICE_ATI_RV530_RADEON_X16003,	R_520  },
 { DEVICE_ATI_RV530_RADEON_X16004,	R_520  },
 { DEVICE_ATI_R580_RADEON_X1900,	R_520  },
 { DEVICE_ATI_R580_RADEON_X19002,	R_520  },
 { DEVICE_ATI_R580_RADEON_X19003,	R_520  },
 { DEVICE_ATI_R580_RADEON_X19004,	R_520  },
 { DEVICE_ATI_R580_RADEON_X19005,	R_520  },
 { DEVICE_ATI_R580_RADEON_X19006,	R_520  },
 { DEVICE_ATI_R580_RADEON_X19007,	R_520  },
 { DEVICE_ATI_R580_RADEON_X19008,	R_520  },
 { DEVICE_ATI_R580_RADEON_X19009,	R_520  },
 { DEVICE_ATI_R580_RADEON_X190010,	R_520  },
 { DEVICE_ATI_R580_RADEON_X190011,	R_520  },
 { DEVICE_ATI_R580_RADEON_X190012,	R_520  },
 { DEVICE_ATI_R580_RADEON_X190013,	R_520  },
 { DEVICE_ATI_R580_RADEON_X190014,	R_520  },
 { DEVICE_ATI_R580_RADEON_X190015,	R_520  },
 { DEVICE_ATI_R580_FIREGL_V7300_V7350,	R_520  },
 { DEVICE_ATI_R580_FIREGL_V7300_V73502,	R_520  },
#endif
};


static void * radeon_mmio_base = 0;
static void * radeon_mem_base = 0; 
static int32_t radeon_overlay_off = 0;
static uint32_t radeon_ram_size = 0;

#define GETREG(TYPE,PTR,OFFZ)		(*((volatile TYPE*)((PTR)+(OFFZ))))
#define SETREG(TYPE,PTR,OFFZ,VAL)	(*((volatile TYPE*)((PTR)+(OFFZ))))=VAL

#define INREG8(addr)		GETREG(uint8_t,(uint8_t *)(radeon_mmio_base),addr)
#define OUTREG8(addr,val)	SETREG(uint8_t,(uint8_t *)(radeon_mmio_base),addr,val)
static inline uint32_t INREG (uint32_t addr) {
    uint32_t tmp = GETREG(uint32_t,(uint8_t *)(radeon_mmio_base),addr);
    return le2me_32(tmp);
}
#define OUTREG(addr,val)	SETREG(uint32_t,(uint8_t *)(radeon_mmio_base),addr,le2me_32(val))
#define OUTREGP(addr,val,mask)						\
	do {								\
		unsigned int _tmp = INREG(addr);			\
		_tmp &= (mask);						\
		_tmp |= (val);						\
		OUTREG(addr, _tmp);					\
	} while (0)

static __inline__ uint32_t INPLL(uint32_t addr)
{
	OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f);
	return (INREG(CLOCK_CNTL_DATA));
}

#define OUTPLL(addr,val)	OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
				OUTREG(CLOCK_CNTL_DATA, val)
#define OUTPLLP(addr,val,mask)						\
	do {								\
		unsigned int _tmp = INPLL(addr);			\
		_tmp &= (mask);						\
		_tmp |= (val);						\
		OUTPLL(addr, _tmp);					\
	} while (0)

#ifndef RAGE128
enum radeon_montype
{
    MT_NONE,
    MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */
    MT_LCD, /* Liquid Crystal Display */
    MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */
    MT_CTV, /* Composite TV out (not in VE) */
    MT_STV  /* S-Video TV out (probably in VE only) */
};

typedef struct radeon_info_s
{
	int hasCRTC2;
	int crtDispType;
	int dviDispType;
}rinfo_t;

static rinfo_t rinfo;

static char * GET_MON_NAME(int type)
{
  char *pret;
  switch(type)
  {
    case MT_NONE: pret = "no"; break;
    case MT_CRT:  pret = "CRT"; break;
    case MT_DFP:  pret = "DFP"; break;
    case MT_LCD:  pret = "LCD"; break;
    case MT_CTV:  pret = "CTV"; break;
    case MT_STV:  pret = "STV"; break;
    default:	  pret = "Unknown";
  }
  return pret;
}

static void radeon_get_moninfo (rinfo_t *rinfo)
{
	unsigned int tmp;

	tmp = INREG(RADEON_BIOS_4_SCRATCH);

	if (rinfo->hasCRTC2) {
		/* primary DVI port */
		if (tmp & 0x08)
			rinfo->dviDispType = MT_DFP;
		else if (tmp & 0x4)
			rinfo->dviDispType = MT_LCD;
		else if (tmp & 0x200)
			rinfo->dviDispType = MT_CRT;
		else if (tmp & 0x10)
			rinfo->dviDispType = MT_CTV;
		else if (tmp & 0x20)
			rinfo->dviDispType = MT_STV;

		/* secondary CRT port */
		if (tmp & 0x2)
			rinfo->crtDispType = MT_CRT;
		else if (tmp & 0x800)
			rinfo->crtDispType = MT_DFP;
		else if (tmp & 0x400)
			rinfo->crtDispType = MT_LCD;
		else if (tmp & 0x1000)
			rinfo->crtDispType = MT_CTV;
		else if (tmp & 0x2000)
			rinfo->crtDispType = MT_STV;
	} else {
		rinfo->dviDispType = MT_NONE;

		tmp = INREG(FP_GEN_CNTL);

		if (tmp & FP_EN_TMDS)
			rinfo->crtDispType = MT_DFP;
		else
			rinfo->crtDispType = MT_CRT;
	}
}
#endif

static uint32_t radeon_vid_get_dbpp( void )
{
  uint32_t dbpp,retval;
  dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF;
  switch(dbpp)
  {
    case DST_8BPP: retval = 8; break;
    case DST_15BPP: retval = 15; break;
    case DST_16BPP: retval = 16; break;
    case DST_24BPP: retval = 24; break;
    default: retval=32; break;
  }
  return retval;
}

static int radeon_is_dbl_scan( void )
{
  return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN;
}

static int radeon_is_interlace( void )
{
  return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN;
}

static uint32_t radeon_get_xres( void )
{
  uint32_t xres,h_total;
#ifndef RAGE128
  if(rinfo.hasCRTC2 && 
       (rinfo.dviDispType == MT_CTV || rinfo.dviDispType == MT_STV))
	h_total = INREG(CRTC2_H_TOTAL_DISP);
  else
#endif
	h_total = INREG(CRTC_H_TOTAL_DISP);
  xres = (h_total >> 16) & 0xffff;
  return (xres + 1)*8;
}

static uint32_t radeon_get_yres( void )
{
  uint32_t yres,v_total;
#ifndef RAGE128
  if(rinfo.hasCRTC2 && 
       (rinfo.dviDispType == MT_CTV || rinfo.dviDispType == MT_STV))
	v_total = INREG(CRTC2_V_TOTAL_DISP);
  else
#endif
	v_total = INREG(CRTC_V_TOTAL_DISP);
  yres = (v_total >> 16) & 0xffff;
  return yres + 1;
}

static void radeon_wait_vsync(void)
{
    int i;

    OUTREG(GEN_INT_STATUS, VSYNC_INT_AK);
    for (i = 0; i < 2000000; i++) 
    {
	if (INREG(GEN_INT_STATUS) & VSYNC_INT) break;
    }
}

#ifdef RAGE128
static void _radeon_engine_idle(void);
static void _radeon_fifo_wait(unsigned);
#define radeon_engine_idle()		_radeon_engine_idle()
#define radeon_fifo_wait(entries)	_radeon_fifo_wait(entries)
/* Flush all dirty data in the Pixel Cache to memory. */
static __inline__ void radeon_engine_flush ( void )
{
    unsigned i;

    OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL);
    for (i = 0; i < 2000000; i++) {
	if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break;
    }
}

/* Reset graphics card to known state. */
static void radeon_engine_reset( void )
{
    uint32_t clock_cntl_index;
    uint32_t mclk_cntl;
    uint32_t gen_reset_cntl;

    radeon_engine_flush();

    clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
    mclk_cntl	     = INPLL(MCLK_CNTL);

    OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP);

    gen_reset_cntl   = INREG(GEN_RESET_CNTL);

    OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
    INREG(GEN_RESET_CNTL);
    OUTREG(GEN_RESET_CNTL,
	gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI));
    INREG(GEN_RESET_CNTL);

    OUTPLL(MCLK_CNTL,	     mclk_cntl);
    OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
    OUTREG(GEN_RESET_CNTL,   gen_reset_cntl);
}
#else

static __inline__ void radeon_engine_flush ( void )