radeon_vid.c

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    bes_flags = SCALER_ENABLE |
                SCALER_SMART_SWITCH |
		SCALER_Y2R_TEMP |
		SCALER_PIX_EXPAND;
#endif
    if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER;
    if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT;
#ifdef RAGE128
    bes_flags |= SCALER_BURST_PER_PLANE;
#endif
    switch(besr.fourcc)
    {
        case IMGFMT_RGB15:
        case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break;
        case IMGFMT_RGB16:
	case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break;
        case IMGFMT_RGB24:
        case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break;
        case IMGFMT_RGB32:
	case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break;
        /* 4:1:0*/
	case IMGFMT_IF09:
        case IMGFMT_YVU9:  bes_flags |= SCALER_SOURCE_YUV9; break;
        /* 4:2:0 */
	case IMGFMT_IYUV:
	case IMGFMT_I420:
	case IMGFMT_YV12:  bes_flags |= SCALER_SOURCE_YUV12;
			   break;
        /* 4:2:2 */
	case IMGFMT_UYVY:  bes_flags |= SCALER_SOURCE_YVYU422; break;
	case IMGFMT_YUY2:
	default:           bes_flags |= SCALER_SOURCE_VYUY422; break;
    }
    OUTREG(OV0_SCALE_CNTL,		bes_flags);
    OUTREG(OV0_REG_LOAD_CNTL,		0);
#ifdef DEBUG
    radeon_vid_dump_regs();
#endif
}

void radeon_vid_set_color_key(int ckey_on, uint8_t R, uint8_t G, uint8_t B)
{
    besr.ckey_on = ckey_on;
    besr.graphics_key_msk=(1ULL<<radeon_vid_get_dbpp()) - 1;
    besr.graphics_key_clr=(R<<16)|(G<<8)|(B)|(0x00 << 24);
}


#define XXX_SRC_X   0
#define XXX_SRC_Y   0

static int radeon_vid_init_video( mga_vid_config_t *config )
{
    uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top;
    int is_420;
RTRACE(RVID_MSG"usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n"
	,(uint32_t)config->version
	,(uint32_t)config->format
	,(uint32_t)config->card_type
	,(uint32_t)config->ram_size
	,(uint32_t)config->src_width
	,(uint32_t)config->src_height
	,(uint32_t)config->x_org
	,(uint32_t)config->y_org
	,(uint32_t)config->dest_width
	,(uint32_t)config->dest_height
	,(uint32_t)config->frame_size
	,(uint32_t)config->num_frames);
    radeon_vid_stop_video();
    left = XXX_SRC_X << 16;
    top = XXX_SRC_Y << 16;
    src_h = config->src_height;
    src_w = config->src_width;
    switch(config->format)
    {
        case IMGFMT_RGB15:
        case IMGFMT_BGR15:
        case IMGFMT_RGB16:
	case IMGFMT_BGR16:
        case IMGFMT_RGB24:
        case IMGFMT_BGR24:
        case IMGFMT_RGB32:
	case IMGFMT_BGR32:
	/* 4:1:0 */
	case IMGFMT_IF09:
        case IMGFMT_YVU9:
	/* 4:2:0 */	
	case IMGFMT_IYUV:
	case IMGFMT_YV12:
	case IMGFMT_I420:
	/* 4:2:2 */
	case IMGFMT_UYVY:
	case IMGFMT_YUY2:
				break;
	default:
		printk(RVID_MSG"Unsupported pixel format: 0x%X\n",config->format);
		return -1;
    }
    is_420 = 0;
    if(config->format == IMGFMT_YV12 ||
       config->format == IMGFMT_I420 ||
       config->format == IMGFMT_IYUV) is_420 = 1;
    switch(config->format)
    {
	/* 4:1:0 */
        case IMGFMT_YVU9:
        case IMGFMT_IF09:
	/* 4:2:0 */
	case IMGFMT_IYUV:
	case IMGFMT_YV12:
	case IMGFMT_I420: pitch = (src_w + 31) & ~31; break;
	/* 4:2:2 */
        default:
	case IMGFMT_UYVY:
	case IMGFMT_YUY2:
        case IMGFMT_RGB15:
        case IMGFMT_BGR15:
        case IMGFMT_RGB16:
	case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break;
        case IMGFMT_RGB24:
        case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break;
        case IMGFMT_RGB32:
	case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break;
    }
    if(radeon_is_dbl_scan()) config->dest_height *= 2;
    else
    if(radeon_is_interlace()) config->dest_height /= 2;
    besr.dest_bpp = radeon_vid_get_dbpp();
    besr.fourcc = config->format;
    besr.v_inc = (src_h << 20) / config->dest_height;
    h_inc = (src_w << 12) / config->dest_width;
    step_by = 1;

    while(h_inc >= (2 << 12)) {
	step_by++;
	h_inc >>= 1;
    }

    /* keep everything in 16.16 */
    besr.base_addr = radeon_mem_base;
    if(is_420)
    {
        uint32_t d1line,d2line,d3line;
	d1line = top*pitch;
	d2line = src_h*pitch+(d1line>>1);
	d3line = d2line+((src_h*pitch)>>2);
	d1line += (left >> 16) & ~15;
	d2line += (left >> 17) & ~15;
	d3line += (left >> 17) & ~15;
        besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK);
        besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL;
        besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL;
	if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV)
	{
	  uint32_t tmp;
	  tmp = besr.vid_buf1_base_adrs;
	  besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs;
	  besr.vid_buf2_base_adrs = tmp;
	}
    }
    else
    {
      besr.vid_buf0_base_adrs = radeon_overlay_off;
      besr.vid_buf0_base_adrs += ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK;
      besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs;
      besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs;
    }
    besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size;
    besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size;
    besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size;

    tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3);
    besr.p1_h_accum_init = ((tmp <<  4) & 0x000f8000) |
			   ((tmp << 12) & 0xf0000000);

    tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2);
    besr.p23_h_accum_init = ((tmp <<  4) & 0x000f8000) |
			    ((tmp << 12) & 0x70000000);
    tmp = (top & 0x0000ffff) + 0x00018000;
    besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK)
			    |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1);

    tmp = ((top >> 1) & 0x0000ffff) + 0x00018000;
    besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK)
			    |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0;

    leftUV = (left >> 17) & 15;
    left = (left >> 16) & 15;
    besr.h_inc = h_inc | ((h_inc >> 1) << 16);
    besr.step_by = step_by | (step_by << 8);
    besr.y_x_start = (config->x_org+X_ADJUST) | (config->y_org << 16);
    besr.y_x_end = (config->x_org + config->dest_width+X_ADJUST) | ((config->y_org + config->dest_height) << 16);
    besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16);
    if(is_420)
    {
	src_h = (src_h + 1) >> 1;
	besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16);
    }
    else besr.p23_blank_lines_at_top = 0;
    besr.vid_buf_pitch0_value = pitch;
    besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch;
    besr.p1_x_start_end = (src_w+left-1)|(left<<16);
    src_w>>=1;
    besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16);
    besr.p3_x_start_end = besr.p2_x_start_end;
    return 0;
}

static void radeon_vid_frame_sel(int frame)
{
    uint32_t off0,off1,off2;
    if(!besr.double_buff) return;
    if(frame%2)
    {
      off0 = besr.vid_buf3_base_adrs;
      off1 = besr.vid_buf4_base_adrs;
      off2 = besr.vid_buf5_base_adrs;
    }
    else
    {
      off0 = besr.vid_buf0_base_adrs;
      off1 = besr.vid_buf1_base_adrs;
      off2 = besr.vid_buf2_base_adrs;
    }
    OUTREG(OV0_REG_LOAD_CNTL,		REG_LD_CTL_LOCK);
    while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK));
    OUTREG(OV0_VID_BUF0_BASE_ADRS,	off0);
    OUTREG(OV0_VID_BUF1_BASE_ADRS,	off1);
    OUTREG(OV0_VID_BUF2_BASE_ADRS,	off2);
    OUTREG(OV0_REG_LOAD_CNTL,		0);
}

static void radeon_vid_make_default(void)
{
#ifdef RAGE128
  OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */
#else
  make_default_gamma_correction();
#endif
  besr.deinterlace_pattern = 0x900AAAAA;
  OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
  besr.deinterlace_on=1;
  besr.double_buff=1;
}


static void radeon_vid_preset(void)
{
#ifdef RAGE128
  unsigned tmp;
  tmp = INREG(OV0_COLOUR_CNTL);
  besr.saturation = (tmp>>8)&0x1f;
  besr.brightness = tmp & 0x7f;
#endif
  besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR);
  besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN);
}

static int video_on = 0;

static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
{
	int frame;

	switch(cmd)
	{
		case MGA_VID_CONFIG:
			RTRACE(RVID_MSG"radeon_mmio_base = %p\n",radeon_mmio_base);
			RTRACE(RVID_MSG"radeon_mem_base = %08x\n",radeon_mem_base);
			RTRACE(RVID_MSG"Received configuration\n");

 			if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t)))
			{
				printk(RVID_MSG"failed copy from userspace\n");
				return -EFAULT;
			}
			if(radeon_config.version != MGA_VID_VERSION){
				printk(RVID_MSG"incompatible version! driver: %X  requested: %X\n",MGA_VID_VERSION,radeon_config.version);
				return -EFAULT;
			}

			if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){
				printk(RVID_MSG"illegal frame_size: %d\n",radeon_config.frame_size);
				return -EFAULT;
			}

			if(radeon_config.num_frames<1){
				printk(RVID_MSG"illegal num_frames: %d\n",radeon_config.num_frames);
				return -EFAULT;
			}
			if(radeon_config.num_frames==1) besr.double_buff=0;
			if(!besr.double_buff) radeon_config.num_frames=1;
			else                  radeon_config.num_frames=2;
			radeon_config.card_type = 0;
			radeon_config.ram_size = radeon_ram_size;
			radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames;
			radeon_overlay_off &= 0xffff0000;
			if(radeon_overlay_off < 0){
			    printk(RVID_MSG"not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000);
			    return -EFAULT;
			}
			RTRACE(RVID_MSG"using video overlay at offset %08X\n",radeon_overlay_off);
			if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t)))
			{
				printk(RVID_MSG"failed copy to userspace\n");
				return -EFAULT;
			}
			radeon_vid_set_color_key(radeon_config.colkey_on,
						 radeon_config.colkey_red,
						 radeon_config.colkey_green,
						 radeon_config.colkey_blue);
			if(swap_fourcc) radeon_config.format = swab32(radeon_config.format); 
			printk(RVID_MSG"configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format));
			return radeon_vid_init_video(&radeon_config);
		break;

		case MGA_VID_ON:
			RTRACE(RVID_MSG"Video ON (ioctl)\n");
			radeon_vid_display_video();
			video_on = 1;
		break;

		case MGA_VID_OFF:
			RTRACE(RVID_MSG"Video OFF (ioctl)\n");
			if(video_on) radeon_vid_stop_video();
			video_on = 0;
		break;

		case MGA_VID_FSEL:
			if(copy_from_user(&frame,(int *) arg,sizeof(int)))
			{
				printk(RVID_MSG"FSEL failed copy from userspace\n");
				return(-EFAULT);
			}
			radeon_vid_frame_sel(frame);
		break;

	        default:
			printk(RVID_MSG"Invalid ioctl\n");
			return (-EINVAL);
	}

	return 0;
}

struct ati_card_id_s
{
  const int id;
  const char name[17];
};

const struct ati_card_id_s ati_card_ids[]=
{
#ifdef RAGE128
 /*
    This driver should be compatible with Rage128 (pro) chips.
    (include adaptive deinterlacing!!!).
    Moreover: the same logic can be used with Mach64 chips.
    (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility).
    but they are incompatible by i/o ports. So if enthusiasts will want
    then they can redefine OUTREG and INREG macros and redefine OV0_*
    constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY
    fourccs (422 and 420 formats only).
  */
/* Rage128 Pro GL */
 { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" },
 { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" },
 { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" },
 { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" },
 { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" },
 { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" },
/* Rage128 Pro VR */
 { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" },
 { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" },
 { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" },
 { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" },
 { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" },
 { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" },
 { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" },
 { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" },
 { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" },
 { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" },
 { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" },
 { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" },
 { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" },
 { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" },
 { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" },