radeon.h

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#	define GMC_DST_16BPP_ARGB4444		0x00000f00
#	define GMC_SRC_MONO			0x00000000
#	define GMC_SRC_MONO_LBKGD		0x00001000
#	define GMC_SRC_DSTCOLOR			0x00003000
#	define GMC_BYTE_ORDER_MSB_TO_LSB	0x00000000
#	define GMC_BYTE_ORDER_LSB_TO_MSB	0x00004000
#	define GMC_DP_CONVERSION_TEMP_9300	0x00008000
#	define GMC_DP_CONVERSION_TEMP_6500	0x00000000
#	define GMC_DP_SRC_RECT			0x02000000
#	define GMC_DP_SRC_HOST			0x03000000
#	define GMC_DP_SRC_HOST_BYTEALIGN	0x04000000
#	define GMC_3D_FCN_EN_CLR		0x00000000
#	define GMC_3D_FCN_EN_SET		0x08000000
#	define GMC_DST_CLR_CMP_FCN_LEAVE	0x00000000
#	define GMC_DST_CLR_CMP_FCN_CLEAR	0x10000000
#	define GMC_AUX_CLIP_LEAVE		0x00000000
#	define GMC_AUX_CLIP_CLEAR		0x20000000
#	define GMC_WRITE_MASK_LEAVE		0x00000000
#	define GMC_WRITE_MASK_SET		0x40000000
#	define GMC_CLR_CMP_CNTL_DIS		(1 << 28)
#	define GMC_SRC_DATATYPE_COLOR		(3 << 12)
#	define ROP3_S				0x00cc0000
#	define ROP3_SRCCOPY			0x00cc0000
#	define ROP3_P				0x00f00000
#	define ROP3_PATCOPY			0x00f00000
#	define DP_SRC_SOURCE_MASK		(7    << 24)
#	define GMC_BRUSH_NONE			(15   <<  4)
#	define DP_SRC_SOURCE_MEMORY		(2    << 24)
#	define GMC_BRUSH_SOLIDCOLOR		0x000000d0
#define	SC_TOP_LEFT				0x16EC
#define	SC_BOTTOM_RIGHT				0x16F0
#define	SRC_SC_BOTTOM_RIGHT			0x16F4
#define	RB2D_DSTCACHE_CTLSTAT			0x342C
#define	RB2D_DSTCACHE_MODE			0x3428

#define	BASE_CODE				0x0f0b
#define	RADEON_BIOS_0_SCRATCH			0x0010
#define	RADEON_BIOS_1_SCRATCH			0x0014
#define	RADEON_BIOS_2_SCRATCH			0x0018
#define	RADEON_BIOS_3_SCRATCH			0x001c
#define	RADEON_BIOS_4_SCRATCH			0x0020
#define	RADEON_BIOS_5_SCRATCH			0x0024
#define	RADEON_BIOS_6_SCRATCH			0x0028
#define	RADEON_BIOS_7_SCRATCH			0x002c


#define	CLK_PIN_CNTL				0x0001
#define	PPLL_CNTL				0x0002
#	define PPLL_RESET			(1 <<  0)
#	define PPLL_SLEEP			(1 <<  1)
#	define PPLL_ATOMIC_UPDATE_EN		(1 << 16)
#	define PPLL_VGA_ATOMIC_UPDATE_EN	(1 << 17)
#	define PPLL_ATOMIC_UPDATE_VSYNC		(1 << 18)
#define	PPLL_REF_DIV				0x0003
#	define PPLL_REF_DIV_MASK		0x03ff
#	define PPLL_ATOMIC_UPDATE_R		(1 << 15) /* same as _W */
#	define PPLL_ATOMIC_UPDATE_W		(1 << 15) /* same as _R */
#define	PPLL_DIV_0				0x0004
#define	PPLL_DIV_1				0x0005
#define	PPLL_DIV_2				0x0006
#define	PPLL_DIV_3				0x0007
#define	VCLK_ECP_CNTL				0x0008
#define	HTOTAL_CNTL				0x0009
#define	HTOTAL2_CNTL				0x002e /* PLL */
#define	M_SPLL_REF_FB_DIV			0x000a
#define	AGP_PLL_CNTL				0x000b
#define	SPLL_CNTL				0x000c
#define	SCLK_CNTL				0x000d
#define	MPLL_CNTL				0x000e
#define	MCLK_CNTL				0x0012
/* MCLK_CNTL bit constants */
#	define FORCEON_MCLKA			(1 << 16)
#	define FORCEON_MCLKB			(1 << 17)
#	define FORCEON_YCLKA			(1 << 18)
#	define FORCEON_YCLKB			(1 << 19)
#	define FORCEON_MC			(1 << 20)
#	define FORCEON_AIC			(1 << 21)
#define	PLL_TEST_CNTL				0x0013
#define	P2PLL_CNTL				0x002a /* P2PLL	*/
#	define P2PLL_RESET			(1 <<  0)
#	define P2PLL_SLEEP			(1 <<  1)
#	define P2PLL_ATOMIC_UPDATE_EN		(1 << 16)
#	define P2PLL_VGA_ATOMIC_UPDATE_EN	(1 << 17)
#	define P2PLL_ATOMIC_UPDATE_VSYNC	(1 << 18)
#define	P2PLL_DIV_0				0x002c
#	define P2PLL_FB0_DIV_MASK		0x07ff
#	define P2PLL_POST0_DIV_MASK		0x00070000
#define	P2PLL_REF_DIV				0x002B /* PLL */
#	define P2PLL_REF_DIV_MASK		0x03ff
#	define P2PLL_ATOMIC_UPDATE_R		(1 << 15) /* same as _W */
#	define P2PLL_ATOMIC_UPDATE_W		(1 << 15) /* same as _R */

/* masks */

#define	CONFIG_MEMSIZE_MASK		0x1f000000
#define	MEM_CFG_TYPE			0x40000000
#define	DST_OFFSET_MASK			0x003fffff
#define	DST_PITCH_MASK			0x3fc00000
#define	DEFAULT_TILE_MASK		0xc0000000
#define	PPLL_DIV_SEL_MASK		0x00000300
#define	PPLL_FB3_DIV_MASK		0x000007ff
#define	PPLL_POST3_DIV_MASK		0x00070000

#define	GUI_ACTIVE			0x80000000

/* GEN_RESET_CNTL bit constants	*/
#define	SOFT_RESET_GUI				0x00000001
#define	SOFT_RESET_VCLK				0x00000100
#define	SOFT_RESET_PCLK				0x00000200
#define	SOFT_RESET_ECP				0x00000400
#define	SOFT_RESET_DISPENG_XCLK			0x00000800
						
/* RAGE	THEATER	REGISTERS */

#define DMA_VIPH0_COMMAND			0x0A00
#define DMA_VIPH1_COMMAND			0x0A04
#define DMA_VIPH2_COMMAND			0x0A08
#define DMA_VIPH3_COMMAND			0x0A0C
#define DMA_VIPH_STATUS				0x0A10
#define DMA_VIPH_CHUNK_0			0x0A18
#define DMA_VIPH_CHUNK_1_VAL			0x0A1C
#define DMA_VIP0_TABLE_ADDR			0x0A20
#define DMA_VIPH0_ACTIVE			0x0A24
#define DMA_VIP1_TABLE_ADDR			0x0A30
#define DMA_VIPH1_ACTIVE			0x0A34
#define DMA_VIP2_TABLE_ADDR			0x0A40
#define DMA_VIPH2_ACTIVE			0x0A44
#define DMA_VIP3_TABLE_ADDR			0x0A50
#define DMA_VIPH3_ACTIVE			0x0A54
#define DMA_VIPH_ABORT				0x0A88

#define	VIPH_CH0_DATA				0x0c00
#define	VIPH_CH1_DATA				0x0c04
#define	VIPH_CH2_DATA				0x0c08
#define	VIPH_CH3_DATA				0x0c0c
#define	VIPH_CH0_ADDR				0x0c10
#define	VIPH_CH1_ADDR				0x0c14
#define	VIPH_CH2_ADDR				0x0c18
#define	VIPH_CH3_ADDR				0x0c1c
#define	VIPH_CH0_SBCNT				0x0c20
#define	VIPH_CH1_SBCNT				0x0c24
#define	VIPH_CH2_SBCNT				0x0c28
#define	VIPH_CH3_SBCNT				0x0c2c
#define	VIPH_CH0_ABCNT				0x0c30
#define	VIPH_CH1_ABCNT				0x0c34
#define	VIPH_CH2_ABCNT				0x0c38
#define	VIPH_CH3_ABCNT				0x0c3c
#define	VIPH_CONTROL				0x0c40
#define	VIPH_DV_LAT				0x0c44
#define	VIPH_BM_CHUNK				0x0c48
#define	VIPH_DV_INT				0x0c4c
#define	VIPH_TIMEOUT_STAT			0x0c50

#define	VIPH_REG_DATA				0x0084
#define	VIPH_REG_ADDR				0x0080

/* Address Space Rage Theatre Registers	(VIP Access) */
#define	VIP_VIP_VENDOR_DEVICE_ID		0x0000
#define	VIP_VIP_SUB_VENDOR_DEVICE_ID		0x0004
#define	VIP_VIP_COMMAND_STATUS			0x0008
#define	VIP_VIP_REVISION_ID			0x000c
#define	VIP_HW_DEBUG				0x0010
#define	VIP_SW_SCRATCH				0x0014
#define	VIP_I2C_CNTL_0				0x0020
#define	VIP_I2C_CNTL_1				0x0024
#define	VIP_I2C_DATA				0x0028
#define	VIP_INT_CNTL				0x002c
#define	VIP_GPIO_INOUT				0x0030
#define	VIP_GPIO_CNTL				0x0034
#define	VIP_CLKOUT_GPIO_CNTL			0x0038
#define	VIP_RIPINTF_PORT_CNTL			0x003c
#define	VIP_ADC_CNTL				0x0400
#define	VIP_ADC_DEBUG				0x0404
#define	VIP_STANDARD_SELECT			0x0408
#define	VIP_THERMO2BIN_STATUS			0x040c
#define	VIP_COMB_CNTL0				0x0440
#define	VIP_COMB_CNTL1				0x0444
#define	VIP_COMB_CNTL2				0x0448
#define	VIP_COMB_LINE_LENGTH			0x044c
#define	VIP_NOISE_CNTL0				0x0450
#define	VIP_HS_PLINE				0x0480
#define	VIP_HS_DTOINC				0x0484
#define	VIP_HS_PLLGAIN				0x0488
#define	VIP_HS_MINMAXWIDTH			0x048c
#define	VIP_HS_GENLOCKDELAY			0x0490
#define	VIP_HS_WINDOW_LIMIT			0x0494
#define	VIP_HS_WINDOW_OC_SPEED			0x0498
#define	VIP_HS_PULSE_WIDTH			0x049c
#define	VIP_HS_PLL_ERROR			0x04a0
#define	VIP_HS_PLL_FS_PATH			0x04a4
#define	VIP_SG_BLACK_GATE			0x04c0
#define	VIP_SG_SYNCTIP_GATE			0x04c4
#define	VIP_SG_UVGATE_GATE			0x04c8
#define	VIP_LP_AGC_CLAMP_CNTL0			0x0500
#define	VIP_LP_AGC_CLAMP_CNTL1			0x0504
#define	VIP_LP_BRIGHTNESS			0x0508
#define	VIP_LP_CONTRAST				0x050c
#define	VIP_LP_SLICE_LIMIT			0x0510
#define	VIP_LP_WPA_CNTL0			0x0514
#define	VIP_LP_WPA_CNTL1			0x0518
#define	VIP_LP_BLACK_LEVEL			0x051c
#define	VIP_LP_SLICE_LEVEL			0x0520
#define	VIP_LP_SYNCTIP_LEVEL			0x0524
#define	VIP_LP_VERT_LOCKOUT			0x0528
#define	VIP_VS_DETECTOR_CNTL			0x0540
#define	VIP_VS_BLANKING_CNTL			0x0544
#define	VIP_VS_FIELD_ID_CNTL			0x0548
#define	VIP_VS_COUNTER_CNTL			0x054c
#define	VIP_VS_FRAME_TOTAL			0x0550
#define	VIP_VS_LINE_COUNT			0x0554
#define	VIP_CP_PLL_CNTL0			0x0580
#define	VIP_CP_PLL_CNTL1			0x0584
#define	VIP_CP_HUE_CNTL				0x0588
#define	VIP_CP_BURST_GAIN			0x058c
#define	VIP_CP_AGC_CNTL				0x0590
#define	VIP_CP_ACTIVE_GAIN			0x0594
#define	VIP_CP_PLL_STATUS0			0x0598
#define	VIP_CP_PLL_STATUS1			0x059c
#define	VIP_CP_PLL_STATUS2			0x05a0
#define	VIP_CP_PLL_STATUS3			0x05a4
#define	VIP_CP_PLL_STATUS4			0x05a8
#define	VIP_CP_PLL_STATUS5			0x05ac
#define	VIP_CP_PLL_STATUS6			0x05b0
#define	VIP_CP_PLL_STATUS7			0x05b4
#define	VIP_CP_DEBUG_FORCE			0x05b8
#define	VIP_CP_VERT_LOCKOUT			0x05bc
#define	VIP_H_ACTIVE_WINDOW			0x05c0
#define	VIP_V_ACTIVE_WINDOW			0x05c4
#define	VIP_H_VBI_WINDOW			0x05c8
#define	VIP_V_VBI_WINDOW			0x05cc
#define	VIP_VBI_CONTROL				0x05d0
#define	VIP_DECODER_DEBUG_CNTL			0x05d4
#define	VIP_SINGLE_STEP_DATA			0x05d8
#define	VIP_MASTER_CNTL				0x0040
#define	VIP_RGB_CNTL				0x0048
#define	VIP_CLKOUT_CNTL				0x004c
#define	VIP_SYNC_CNTL				0x0050
#define	VIP_I2C_CNTL				0x0054
#define	VIP_HTOTAL				0x0080
#define	VIP_HDISP				0x0084
#define	VIP_HSIZE				0x0088
#define	VIP_HSTART				0x008c
#define	VIP_HCOUNT				0x0090
#define	VIP_VTOTAL				0x0094
#define	VIP_VDISP				0x0098
#define	VIP_VCOUNT				0x009c
#define	VIP_VFTOTAL				0x00a0
#define	VIP_DFCOUNT				0x00a4
#define	VIP_DFRESTART				0x00a8
#define	VIP_DHRESTART				0x00ac
#define	VIP_DVRESTART				0x00b0
#define	VIP_SYNC_SIZE				0x00b4
#define	VIP_TV_PLL_FINE_CNTL			0x00b8
#define	VIP_CRT_PLL_FINE_CNTL			0x00bc
#define	VIP_TV_PLL_CNTL				0x00c0
#define	VIP_CRT_PLL_CNTL			0x00c4
#define	VIP_PLL_CNTL0				0x00c8
#define	VIP_PLL_TEST_CNTL			0x00cc
#define	VIP_CLOCK_SEL_CNTL			0x00d0
#define	VIP_VIN_PLL_CNTL			0x00d4
#define	VIP_VIN_PLL_FINE_CNTL			0x00d8
#define	VIP_AUD_PLL_CNTL			0x00e0
#define	VIP_AUD_PLL_FINE_CNTL			0x00e4
#define	VIP_AUD_CLK_DIVIDERS			0x00e8
#define	VIP_AUD_DTO_INCREMENTS			0x00ec
#define	VIP_L54_PLL_CNTL			0x00f0
#define	VIP_L54_PLL_FINE_CNTL			0x00f4
#define	VIP_L54_DTO_INCREMENTS			0x00f8
#define	VIP_PLL_CNTL1				0x00fc
#define	VIP_FRAME_LOCK_CNTL			0x0100
#define	VIP_SYNC_LOCK_CNTL			0x0104
#define	VIP_TVO_SYNC_PAT_ACCUM			0x0108
#define	VIP_TVO_SYNC_THRESHOLD			0x010c
#define	VIP_TVO_SYNC_PAT_EXPECT			0x0110
#define	VIP_DELAY_ONE_MAP_A			0x0114
#define	VIP_DELAY_ONE_MAP_B			0x0118
#define	VIP_DELAY_ZERO_MAP_A			0x011c
#define	VIP_DELAY_ZERO_MAP_B			0x0120
#define	VIP_TVO_DATA_DELAY_A			0x0140
#define	VIP_TVO_DATA_DELAY_B			0x0144
#define	VIP_HOST_READ_DATA			0x0180
#define	VIP_HOST_WRITE_DATA			0x0184
#define	VIP_HOST_RD_WT_CNTL			0x0188
#define	VIP_VSCALER_CNTL1			0x01c0
#define	VIP_TIMING_CNTL				0x01c4
#define	VIP_VSCALER_CNTL2			0x01c8
#define	VIP_Y_FALL_CNTL				0x01cc
#define	VIP_Y_RISE_CNTL				0x01d0
#define	VIP_Y_SAW_TOOTH_CNTL			0x01d4
#define	VIP_UPSAMP_AND_GAIN_CNTL		0x01e0
#define	VIP_GAIN_LIMIT_SETTINGS			0x01e4
#define	VIP_LINEAR_GAIN_SETTINGS		0x01e8
#define	VIP_MODULATOR_CNTL1			0x0200
#define	VIP_MODULATOR_CNTL2			0x0204
#define	VIP_MV_MODE_CNTL			0x0208
#define	VIP_MV_STRIPE_CNTL			0x020c
#define	VIP_MV_LEVEL_CNTL1			0x0210
#define	VIP_MV_LEVEL_CNTL2			0x0214
#define	VIP_PRE_DAC_MUX_CNTL			0x0240
#define	VIP_TV_DAC_CNTL				0x0280
#define	VIP_CRC_CNTL				0x02c0
#define	VIP_VIDEO_PORT_SIG			0x02c4
#define	VIP_VBI_CC_CNTL				0x02c8
#define	VIP_VBI_EDS_CNTL			0x02cc
#define	VIP_VBI_20BIT_CNTL			0x02d0
#define	VIP_VBI_DTO_CNTL			0x02d4
#define	VIP_VBI_LEVEL_CNTL			0x02d8
#define	VIP_UV_ADR				0x0300
#define	VIP_MV_STATUS				0x0330
#define	VIP_UPSAMP_COEFF0_0			0x0340
#define	VIP_UPSAMP_COEFF0_1			0x0344
#define	VIP_UPSAMP_COEFF0_2			0x0348
#define	VIP_UPSAMP_COEFF1_0			0x034c
#define	VIP_UPSAMP_COEFF1_1			0x0350
#define	VIP_UPSAMP_COEFF1_2			0x0354
#define	VIP_UPSAMP_COEFF2_0			0x0358
#define	VIP_UPSAMP_COEFF2_1			0x035c
#define	VIP_UPSAMP_COEFF2_2			0x0360
#define	VIP_UPSAMP_COEFF3_0			0x0364
#define	VIP_UPSAMP_COEFF3_1			0x0368
#define	VIP_UPSAMP_COEFF3_2			0x036c
#define	VIP_UPSAMP_COEFF4_0			0x0370
#define	VIP_UPSAMP_COEFF4_1			0x0374
#define	VIP_UPSAMP_COEFF4_2			0x0378
#define	VIP_TV_DTO_INCREMENTS			0x0390
#define	VIP_CRT_DTO_INCREMENTS			0x0394
#define	VIP_VSYNC_DIFF_CNTL			0x03a0
#define	VIP_VSYNC_DIFF_LIMITS			0x03a4
#define	VIP_VSYNC_DIFF_RD_DATA			0x03a8
#define	VIP_SCALER_IN_WINDOW			0x0618
#define	VIP_SCALER_OUT_WINDOW			0x061c
#define	VIP_H_SCALER_CONTROL			0x0600
#define	VIP_V_SCALER_CONTROL			0x0604
#define	VIP_V_DEINTERLACE_CONTROL		0x0608
#define	VIP_VBI_SCALER_CONTROL			0x060c
#define	VIP_DVS_PORT_CTRL			0x0610
#define	VIP_DVS_PORT_READBACK			0x0614
#define	VIP_FIFOA_CONFIG			0x0800
#define	VIP_FIFOB_CONFIG			0x0804
#define	VIP_FIFOC_CONFIG			0x0808
#define	VIP_SPDIF_PORT_CNTL			0x080c
#define	VIP_SPDIF_CHANNEL_STAT			0x0810
#define	VIP_SPDIF_AC3_PREAMBLE			0x0814
#define	VIP_I2S_TRANSMIT_CNTL			0x0818
#define	VIP_I2S_RECEIVE_CNTL			0x081c
#define	VIP_SPDIF_TX_CNT_REG			0x0820
#define	VIP_IIS_TX_CNT_REG			0x0824

/* Status defines */
#define	VIP_BUSY	0
#define	VIP_IDLE	1
#define	VIP_RESET	2

#define	VIPH_TIMEOUT_STAT__VIPH_REG_STAT	0x00000010
#define	VIPH_TIMEOUT_STAT__VIPH_REG_AK		0x00000010
#define	VIPH_TIMEOUT_STAT__VIPH_REGR_DIS	0x01000000
#define	TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN	0x00000001

#define	RT_ATI_ID 0x4D541002

/* Register/Field values: */
#define	RT_COMP0				0x0
#define	RT_COMP1				0x1
#define	RT_COMP2				0x2
#define	RT_YF_COMP3				0x3
#define	RT_YR_COMP3				0x4
#define	RT_YCF_COMP4				0x5
#define	RT_YCR_COMP4				0x6

/* Video standard defines */
#define	RT_NTSC					0x0
#define	RT_PAL					0x1
#define	RT_SECAM				0x2