radeon.h

来自「君正早期ucos系统(只有早期的才不没有打包成库),MPLAYER,文件系统,图」· C头文件 代码 · 共 1,862 行 · 第 1/5 页

#define	CRTC_OFFSET_RIGHT			0x0220
#define	CRTC_OFFSET				0x0224
#define	CRTC2_OFFSET				0x0324
#define	CRTC_OFFSET_CNTL			0x0228
#	define CRTC_TILE_EN			(1 << 15)
#define	CRTC2_OFFSET_CNTL			0x0328
#	define CRTC2_TILE_EN			(1 << 15)
#define	CRTC_PITCH				0x022C
#define	CRTC2_PITCH				0x032C
#define	TMDS_CRC				0x02a0
#define	OVR_CLR					0x0230
#define	OVR_WID_LEFT_RIGHT			0x0234
#define	OVR_WID_TOP_BOTTOM			0x0238
#define	DISPLAY_BASE_ADDR			0x023C
#define	SNAPSHOT_VH_COUNTS			0x0240
#define	SNAPSHOT_F_COUNT			0x0244
#define	N_VIF_COUNT				0x0248
#define	SNAPSHOT_VIF_COUNT			0x024C
#define	FP_CRTC_H_TOTAL_DISP			0x0250
#define	FP_CRTC2_H_TOTAL_DISP			0x0350
#define	FP_CRTC_V_TOTAL_DISP			0x0254
#define	FP_CRTC2_V_TOTAL_DISP			0x0354
#	define FP_CRTC_H_TOTAL_MASK		0x000003ff
#	define FP_CRTC_H_DISP_MASK		0x01ff0000
#	define FP_CRTC_V_TOTAL_MASK		0x00000fff
#	define FP_CRTC_V_DISP_MASK		0x0fff0000
#	define FP_H_SYNC_STRT_CHAR_MASK		0x00001ff8
#	define FP_H_SYNC_WID_MASK		0x003f0000
#	define FP_V_SYNC_STRT_MASK		0x00000fff
#	define FP_V_SYNC_WID_MASK		0x001f0000
#	define FP_CRTC_H_TOTAL_SHIFT		0x00000000
#	define FP_CRTC_H_DISP_SHIFT		0x00000010
#	define FP_CRTC_V_TOTAL_SHIFT		0x00000000
#	define FP_CRTC_V_DISP_SHIFT		0x00000010
#	define FP_H_SYNC_STRT_CHAR_SHIFT	0x00000003
#	define FP_H_SYNC_WID_SHIFT		0x00000010
#	define FP_V_SYNC_STRT_SHIFT		0x00000000
#	define FP_V_SYNC_WID_SHIFT		0x00000010
#define	CRT_CRTC_H_SYNC_STRT_WID		0x0258
#define	CRT_CRTC_V_SYNC_STRT_WID		0x025C
#define	CUR_OFFSET				0x0260
#define	CUR_HORZ_VERT_POSN			0x0264
#define	CUR_HORZ_VERT_OFF			0x0268
/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
#	define CUR_LOCK				0x80000000
#define	CUR_CLR0				0x026C
#define	CUR_CLR1				0x0270
#define	CUR2_OFFSET				0x0360
#define	CUR2_HORZ_VERT_POSN			0x0364
#define	CUR2_HORZ_VERT_OFF			0x0368
#	define CUR2_LOCK			(1 << 31)
#define	CUR2_CLR0				0x036c
#define	CUR2_CLR1				0x0370
#define	FP_HORZ_VERT_ACTIVE			0x0278
#define	CRTC_MORE_CNTL				0x027C
#define	DAC_EXT_CNTL				0x0280
#define	FP_GEN_CNTL				0x0284
/* FP_GEN_CNTL bit constants */
#	define FP_FPON				(1 <<  0)
#	define FP_TMDS_EN			(1 <<  2)
#	define FP_EN_TMDS			(1 <<  7)
#	define FP_DETECT_SENSE			(1 <<  8)
#	define FP_SEL_CRTC2			(1 << 13)
#	define FP_CRTC_DONT_SHADOW_HPAR		(1 << 15)
#	define FP_CRTC_DONT_SHADOW_VPAR		(1 << 16)
#	define FP_CRTC_DONT_SHADOW_HEND		(1 << 17)
#	define FP_CRTC_USE_SHADOW_VEND		(1 << 18)
#	define FP_RMX_HVSYNC_CONTROL_EN		(1 << 20)
#	define FP_DFP_SYNC_SEL			(1 << 21)
#	define FP_CRTC_LOCK_8DOT		(1 << 22)
#	define FP_CRT_SYNC_SEL			(1 << 23)
#	define FP_USE_SHADOW_EN			(1 << 24)
#	define FP_CRT_SYNC_ALT			(1 << 26)
#define	FP2_GEN_CNTL				0x0288
/* FP2_GEN_CNTL	bit constants */
#	define FP2_FPON				(1 <<  0)
#	define FP2_TMDS_EN			(1 <<  2)
#	define FP2_EN_TMDS			(1 <<  7)
#	define FP2_DETECT_SENSE			(1 <<  8)
#	define FP2_SEL_CRTC2			(1 << 13)
#	define FP2_FP_POL			(1 << 16)
#	define FP2_LP_POL			(1 << 17)
#	define FP2_SCK_POL			(1 << 18)
#	define FP2_LCD_CNTL_MASK		(7 << 19)
#	define FP2_PAD_FLOP_EN			(1 << 22)
#	define FP2_CRC_EN			(1 << 23)
#	define FP2_CRC_READ_EN			(1 << 24)
#define	FP_HORZ_STRETCH				0x028C
#define	FP_HORZ2_STRETCH			0x038C
#	define HORZ_STRETCH_RATIO_MASK		0xffff
#	define HORZ_STRETCH_RATIO_MAX		4096
#	define HORZ_PANEL_SIZE			(0x1ff	 << 16)
#	define HORZ_PANEL_SHIFT			16
#	define HORZ_STRETCH_PIXREP		(0	<< 25)
#	define HORZ_STRETCH_BLEND		(1	<< 26)
#	define HORZ_STRETCH_ENABLE		(1	<< 25)
#	define HORZ_AUTO_RATIO			(1	<< 27)
#	define HORZ_FP_LOOP_STRETCH		(0x7	<< 28)
#	define HORZ_AUTO_RATIO_INC		(1	<< 31)
#define	FP_VERT_STRETCH				0x0290
#define	FP_VERT2_STRETCH			0x0390
#	define VERT_PANEL_SIZE			(0xfff << 12)
#	define VERT_PANEL_SHIFT			12
#	define VERT_STRETCH_RATIO_MASK		0xfff
#	define VERT_STRETCH_RATIO_SHIFT		0
#	define VERT_STRETCH_RATIO_MAX		4096
#	define VERT_STRETCH_ENABLE		(1     << 25)
#	define VERT_STRETCH_LINEREP		(0     << 26)
#	define VERT_STRETCH_BLEND		(1     << 26)
#	define VERT_AUTO_RATIO_EN		(1     << 27)
#	define VERT_STRETCH_RESERVED		0xf1000000
#define	FP_H_SYNC_STRT_WID			0x02C4
#define	FP_H2_SYNC_STRT_WID			0x03C4
#define	FP_V_SYNC_STRT_WID			0x02C8
#define	FP_V2_SYNC_STRT_WID			0x03C8
#define	LVDS_GEN_CNTL				0x02d0
#	define LVDS_ON				(1   <<	 0)
#	define LVDS_DISPLAY_DIS			(1   <<	 1)
#	define LVDS_PANEL_TYPE			(1   <<	 2)
#	define LVDS_PANEL_FORMAT		(1   <<	 3)
#	define LVDS_EN				(1   <<	 7)
#	define LVDS_DIGON			(1   <<	18)
#	define LVDS_BLON			(1   <<	19)
#	define LVDS_SEL_CRTC2			(1   <<	23)
#define	LVDS_PLL_CNTL				0x02d4
#	define HSYNC_DELAY_SHIFT		28
#	define HSYNC_DELAY_MASK			(0xf <<	28)
#define	AUX_WINDOW_HORZ_CNTL			0x02D8
#define	AUX_WINDOW_VERT_CNTL			0x02DC
#define	DDA_CONFIG				0x02e0
#define	DDA_ON_OFF				0x02e4

#define	GRPH_BUFFER_CNTL			0x02F0
#define	VGA_BUFFER_CNTL				0x02F4

/* first overlay unit (there is only one) */

#define	OV0_Y_X_START				0x0400
#define	OV0_Y_X_END				0x0404
#define	OV0_PIPELINE_CNTL			0x0408
#define	OV0_EXCLUSIVE_HORZ			0x0408
#	define EXCL_HORZ_START_MASK		0x000000ff
#	define EXCL_HORZ_END_MASK		0x0000ff00
#	define EXCL_HORZ_BACK_PORCH_MASK	0x00ff0000
#	define EXCL_HORZ_EXCLUSIVE_EN		0x80000000
#define	OV0_EXCLUSIVE_VERT			0x040C
#	define EXCL_VERT_START_MASK		0x000003ff
#	define EXCL_VERT_END_MASK		0x03ff0000
#define	OV0_REG_LOAD_CNTL			0x0410
#	define REG_LD_CTL_LOCK			0x00000001L
#	define REG_LD_CTL_VBLANK_DURING_LOCK	0x00000002L
#	define REG_LD_CTL_STALL_GUI_UNTIL_FLIP	0x00000004L
#	define REG_LD_CTL_LOCK_READBACK		0x00000008L
#define	OV0_SCALE_CNTL				0x0420
#	define SCALER_PIX_EXPAND		0x00000001L
#	define SCALER_Y2R_TEMP			0x00000002L
#ifdef RAGE128
#	define SCALER_HORZ_PICK_NEAREST		0x00000003L
#	define SCALER_VERT_PICK_NEAREST		0x00000004L
#else
#	define SCALER_HORZ_PICK_NEAREST		0x00000004L
#	define SCALER_VERT_PICK_NEAREST		0x00000008L
#endif
#	define SCALER_SIGNED_UV			0x00000010L
#	define SCALER_GAMMA_SEL_MASK		0x00000060L
#	define SCALER_GAMMA_SEL_BRIGHT		0x00000000L
#	define SCALER_GAMMA_SEL_G22		0x00000020L
#	define SCALER_GAMMA_SEL_G18		0x00000040L
#	define SCALER_GAMMA_SEL_G14		0x00000060L
#	define SCALER_COMCORE_SHIFT_UP_ONE	0x00000080L
#	define SCALER_SURFAC_FORMAT		0x00000f00L
#	define SCALER_SOURCE_UNK0		0x00000000L /* 2 bpp ??? */
#	define SCALER_SOURCE_UNK1		0x00000100L /* 4 bpp ??? */
#	define SCALER_SOURCE_UNK2		0x00000200L /* 8 bpp ??? */
#	define SCALER_SOURCE_15BPP		0x00000300L
#	define SCALER_SOURCE_16BPP		0x00000400L
#	define SCALER_SOURCE_24BPP		0x00000500L
#	define SCALER_SOURCE_32BPP		0x00000600L
#	define SCALER_SOURCE_UNK3		0x00000700L /* 8BPP_RGB332 ??? */
#	define SCALER_SOURCE_UNK4		0x00000800L /* 8BPP_Y8 ??? */
#	define SCALER_SOURCE_YUV9		0x00000900L /* 8BPP_RGB8 */
#	define SCALER_SOURCE_YUV12		0x00000A00L
#	define SCALER_SOURCE_VYUY422		0x00000B00L
#	define SCALER_SOURCE_YVYU422		0x00000C00L
#	define SCALER_SOURCE_UNK5		0x00000D00L /* ??? */
#	define SCALER_SOURCE_UNK6		0x00000E00L /* 32BPP_AYUV444 */
#	define SCALER_SOURCE_UNK7		0x00000F00L /* 16BPP_ARGB4444 */
#	define SCALER_ADAPTIVE_DEINT		0x00001000L
#	define R200_SCALER_TEMPORAL_DEINT	0x00002000L
#	define SCALER_UNKNOWN_FLAG1		0x00004000L /* ??? */
#	define SCALER_SMART_SWITCH		0x00008000L
#ifdef RAGE128
#	define SCALER_BURST_PER_PLANE		0x00ff0000L
#else
#	define SCALER_BURST_PER_PLANE		0x007f0000L
#endif
#	define SCALER_DOUBLE_BUFFER		0x01000000L
#	define SCALER_UNKNOWN_FLAG3		0x02000000L /* ??? */
#	define SCALER_UNKNOWN_FLAG4		0x04000000L /* ??? */
#	define SCALER_DIS_LIMIT			0x08000000L
#	define SCALER_PRG_LOAD_START		0x10000000L
#	define SCALER_INT_EMU			0x20000000L
#	define SCALER_ENABLE			0x40000000L
#	define SCALER_SOFT_RESET		0x80000000L
#define	OV0_V_INC				0x0424
#define	OV0_P1_V_ACCUM_INIT			0x0428
#	define OV0_P1_MAX_LN_IN_PER_LN_OUT	0x00000003L
#	define OV0_P1_V_ACCUM_INIT_MASK		0x01ff8000L
#define	OV0_P23_V_ACCUM_INIT			0x042C
#	define OV0_P23_MAX_LN_IN_PER_LN_OUT	0x00000003L
#	define OV0_P23_V_ACCUM_INIT_MASK	0x01ff8000L
#define	OV0_P1_BLANK_LINES_AT_TOP		0x0430
#	define P1_BLNK_LN_AT_TOP_M1_MASK	0x00000fffL
#	define P1_ACTIVE_LINES_M1		0x0fff0000L
#define	OV0_P23_BLANK_LINES_AT_TOP		0x0434
#	define P23_BLNK_LN_AT_TOP_M1_MASK	0x000007ffL
#	define P23_ACTIVE_LINES_M1		0x07ff0000L
#ifndef RAGE128
#define	OV0_BASE_ADDR				0x043C
#endif
#define	OV0_VID_BUF0_BASE_ADRS			0x0440
#	define VIF_BUF0_PITCH_SEL		0x00000001L
#	define VIF_BUF0_TILE_ADRS		0x00000002L
#	define VIF_BUF0_BASE_ADRS_MASK		0x03fffff0L
#	define VIF_BUF0_1ST_LINE_LSBS_MASK	0x48000000L
#define	OV0_VID_BUF1_BASE_ADRS			0x0444
#	define VIF_BUF1_PITCH_SEL		0x00000001L
#	define VIF_BUF1_TILE_ADRS		0x00000002L
#	define VIF_BUF1_BASE_ADRS_MASK		0x03fffff0L
#	define VIF_BUF1_1ST_LINE_LSBS_MASK	0x48000000L
#define	OV0_VID_BUF2_BASE_ADRS			0x0448
#	define VIF_BUF2_PITCH_SEL		0x00000001L
#	define VIF_BUF2_TILE_ADRS		0x00000002L
#	define VIF_BUF2_BASE_ADRS_MASK		0x03fffff0L
#	define VIF_BUF2_1ST_LINE_LSBS_MASK	0x48000000L
#define	OV0_VID_BUF3_BASE_ADRS			0x044C
#	define VIF_BUF3_PITCH_SEL		0x00000001L
#	define VIF_BUF3_TILE_ADRS		0x00000002L
#	define VIF_BUF3_BASE_ADRS_MASK		0x03fffff0L
#	define VIF_BUF3_1ST_LINE_LSBS_MASK	0x48000000L
#define	OV0_VID_BUF4_BASE_ADRS			0x0450
#	define VIF_BUF4_PITCH_SEL		0x00000001L
#	define VIF_BUF4_TILE_ADRS		0x00000002L
#	define VIF_BUF4_BASE_ADRS_MASK		0x03fffff0L
#	define VIF_BUF4_1ST_LINE_LSBS_MASK	0x48000000L
#define	OV0_VID_BUF5_BASE_ADRS			0x0454
#	define VIF_BUF5_PITCH_SEL		0x00000001L
#	define VIF_BUF5_TILE_ADRS		0x00000002L
#	define VIF_BUF5_BASE_ADRS_MASK		0x03fffff0L
#	define VIF_BUF5_1ST_LINE_LSBS_MASK	0x48000000L
#define	OV0_VID_BUF_PITCH0_VALUE		0x0460
#define	OV0_VID_BUF_PITCH1_VALUE		0x0464
#define	OV0_AUTO_FLIP_CNTL			0x0470
#	define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM		0x00000007
#	define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD	0x00000008
#	define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD		0x00000010
#	define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD	0x00000020
#	define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE	0x00000040
#	define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT	0x00000300
#	define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN	0x00010000
#	define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN	0x00040000
#	define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN	0x00080000
#	define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE	0x00800000
#define	OV0_DEINTERLACE_PATTERN			0x0474
#define	OV0_SUBMIT_HISTORY			0x0478
#define	OV0_H_INC				0x0480
#define	OV0_STEP_BY				0x0484
#define	OV0_P1_H_ACCUM_INIT			0x0488
#define	OV0_P23_H_ACCUM_INIT			0x048C
#define	OV0_P1_X_START_END			0x0494
#define	OV0_P2_X_START_END			0x0498
#define	OV0_P3_X_START_END			0x049C
#define	OV0_FILTER_CNTL				0x04A0
#	define FILTER_PROGRAMMABLE_COEF		0x00000000
#	define FILTER_HARDCODED_COEF		0x0000000F
#	define FILTER_COEF_MASK			0x0000000F
/* other values allow us use hardcoded coefs for Y and
   programmable for UV that's nosense. */
/*
   Top quality 4x4-tap filtered vertical and horizontal scaler.
   It allows up to 64:1 upscaling and downscaling without
   performance or quality degradation.
*/
#define	OV0_FOUR_TAP_COEF_0			0x04B0
#define	OV0_FOUR_TAP_COEF_1			0x04B4
#define	OV0_FOUR_TAP_COEF_2			0x04B8
#define	OV0_FOUR_TAP_COEF_3			0x04BC
#define	OV0_FOUR_TAP_COEF_4			0x04C0

#define	OV0_FLAG_CNTL				0x04DC
#ifdef RAGE128
#define	OV0_COLOUR_CNTL				0x04E0
#	define COLOUR_CNTL_BRIGHTNESS		0x0000007F
#	define COLOUR_CNTL_SATURATION		0x001F1F00
#else
/* NB: radeons have no COLOUR_CNTL register */
#define	OV0_SLICE_CNTL				0x04E0
#	define SLICE_CNTL_DISABLE		0x40000000
#endif
/* Video and graphics keys allow alpha blending, color correction
   and many other video effects */
#define	OV0_VID_KEY_CLR				0x04E4
#define	OV0_VID_KEY_MSK				0x04E8
#define	OV0_GRAPHICS_KEY_CLR			0x04EC
#define	OV0_GRAPHICS_KEY_MSK			0x04F0
#define	OV0_KEY_CNTL				0x04F4
#	define VIDEO_KEY_FN_MASK		0x00000007L
#	define VIDEO_KEY_FN_FALSE		0x00000000L
#	define VIDEO_KEY_FN_TRUE		0x00000001L
#	define VIDEO_KEY_FN_EQ			0x00000004L
#	define VIDEO_KEY_FN_NE			0x00000005L
#	define GRAPHIC_KEY_FN_MASK		0x00000070L
#	define GRAPHIC_KEY_FN_FALSE		0x00000000L
#	define GRAPHIC_KEY_FN_TRUE		0x00000010L
#	define GRAPHIC_KEY_FN_EQ		0x00000040L
#	define GRAPHIC_KEY_FN_NE		0x00000050L
#	define CMP_MIX_MASK			0x00000100L
#	define CMP_MIX_OR			0x00000000L
#	define CMP_MIX_AND			0x00000100L
#define	OV0_TEST				0x04F8
#define	OV0_LIN_TRANS_A				0x0D20
#define	OV0_LIN_TRANS_B				0x0D24
#define	OV0_LIN_TRANS_C				0x0D28
#define	OV0_LIN_TRANS_D				0x0D2C
#define	OV0_LIN_TRANS_E				0x0D30
#define	OV0_LIN_TRANS_F				0x0D34
#define	OV0_GAMMA_0_F				0x0D40
#define	OV0_GAMMA_10_1F				0x0D44
#define	OV0_GAMMA_20_3F				0x0D48
#define	OV0_GAMMA_40_7F				0x0D4C
/* These registers exist on R200 only */
#define OV0_GAMMA_80_BF				0x0E00
#define OV0_GAMMA_C0_FF				0x0E04
#define OV0_GAMMA_100_13F			0x0E08
#define OV0_GAMMA_140_17F			0x0E0C
#define OV0_GAMMA_180_1BF			0x0E10
#define OV0_GAMMA_1C0_1FF			0x0E14
#define OV0_GAMMA_200_23F			0x0E18
#define OV0_GAMMA_240_27F			0x0E1C
#define OV0_GAMMA_280_2BF			0x0E20
#define OV0_GAMMA_2C0_2FF			0x0E24
#define OV0_GAMMA_300_33F			0x0E28
#define OV0_GAMMA_340_37F			0x0E2C
/* End of R200 specific definitions */
#define	OV0_GAMMA_380_3BF			0x0D50
#define	OV0_GAMMA_3C0_3FF			0x0D54

/*
 IDCT ENGINE:
 It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag
 and IDCT into an IDCT engine to complement the motion compensation engine.
*/
#define IDCT_RUNS				0x1F80
#define IDCT_LEVELS				0x1F84
#define IDCT_AUTH_CONTROL			0x1F88
#define IDCT_AUTH				0x1F8C
#define IDCT_CONTROL				0x1FBC

#define SE_MC_SRC2_CNTL				0x19D4
#define SE_MC_SRC1_CNTL				0x19D8
#define SE_MC_DST_CNTL				0x19DC
#define SE_MC_CNTL_START			0x19E0
#ifndef RAGE128
#define SE_MC_BUF_BASE				0x19E4
#define PP_MC_CONTEXT				0x19E8
#define PP_MISC					0x1C14
#endif
/*
   SUBPICTURE UNIT:
   Decompressing, scaling and alpha blending the compressed bitmap on the fly.
   Provide optimal DVD subpicture qualtity.
*/
#define	SUBPIC_CNTL				0x0540