jz_spi.c

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#include "jz4740.h"

#define SPI_FIFO 128
#define SSI_FRAME_LENGTH 8
#define CPM_SSICDR ( CPM_BASE+0x74 )
#define REG_CPM_SSICDR  REG32( CPM_SSICDR )


#define __ssi_underrun()                           \
        ( REG_SSI_SR&0x00000002 )

#define __ssi_overrun()                            \
        ( REG_SSI_SR&0x00000001 )

#define __ssi_clear_underrun()                     \
        do{                                        \
            REG_SSI_SR&=0xfffffffd;                \
        }while(0)

#define __ssi_clear_overrun()                      \
        do{                                        \
            REG_SSI_SR&=0xfffffffe;                \
        }while(0)

#define __ssi_get_rfifo_count()                    \
        ( REG_SSI_SR&0x0000ff00 )

#define __ssi_get_tfifo_count()                    \
        ( REG_SSI_SR&0x00ff0000 )

#define __ssi_get_fifo_buff()                      \
        ( REG_SSI_DR )

#define __ssi_set_clk_cgv(x)                       \
        do{                                        \
            REG_SSI_GR |= x;                       \
        }while(0)

#define __cpm_ssiclk_select_pllout()               \
        do{                                        \
            REG_CPM_SSICDR &= (1<<31);             \
        }while(0)
#define __cpm_ssiclk_select_extout()               \
        do{                                        \
            REG_CPM_SSICDR &= (0<<31);             \
        }while(0)

#define __cpm_set_ssidiv(x)                        \
        do{                                        \
            REG_CPM_SSICDR |= x;                   \
        }while(0)



void print_ssi_regs(void )
{
    unsigned int val;
    
    val = REG_SSI_DR;
    printf("REG_SSI_DR: 0x%8.8x\n",val);

    val = REG_SSI_CR0;
    printf("REG_SSI_CR0:0x%8.8x\n", val );

    val = REG_SSI_CR1;
    printf("REG_SSI_CR1:0x%8.8x\n", val );

    val = REG_SSI_SR;
    printf("REG_SSI_SR :0x%8.8x\n", val );

    val = REG_SSI_ITR;
    printf("REG_SSI_ITR:0x%8.8x\n", val );

    val = REG_SSI_ICR;
    printf("REG_SSI_ICR:0x%8.8x\n", val );

    val = REG_SSI_GR;
    printf("REG_SSI_GR :0x%8.8x\n", val );
    printf("===========================\n");
}

//18:clk,19:ce0,20:dt,21:dr

static int reset_gpio()
{
    printf("reset_gpio\n");
    __gpio_as_ssi();
    __gpio_as_output(3*32+18);//clk
    __gpio_as_output(3*32+19);//cs
    __gpio_as_input(3*32+21);
    __gpio_as_output(3*32+20);
   // __gpio_set_pin(3*32+19);
}

int ssi_init_mode_cpu()
{

    __cpm_ssiclk_select_extout();
    //__cpm_set_ssidiv(1);
    __cpm_start_ssi();
    
    __ssi_disable();
    
    
    __ssi_enable();

    printf("ssi_init_mode_cpu\n");
    //__gpio_as_ssi();
    reset_gpio();
    __cpm_ssiclk_select_pllout();
    __cpm_set_ssidiv(1);
    __cpm_start_ssi();

    __ssi_disable();
    __ssi_set_clk_cgv(15);
    __ssi_disable_tx_intr();
    __ssi_disable_rx_intr();
    __ssi_enable_receive();
    __ssi_flush_fifo();
    __ssi_clear_errors();
    __ssi_spi_format();
    __ssi_set_spi_clock_phase(0);     //PHA = 1
    __ssi_set_spi_clock_polarity(0);  //POL = 0
    __ssi_set_msb();
    __ssi_set_frame_length(8);
    __ssi_disable_loopback(); /* just for test */
     __ssi_select_ce();
    __ssi_set_tx_trigger(64);  /* total 128 entries */
    __ssi_set_rx_trigger(8);  /* total 128 entries */
    __ssi_enable();

    print_ssi_regs();
    return 1;
}

int spi_read_mb_cpu(char *buf, int size)
{
    printf("spi_read_mb_cpu\n");
    if( __ssi_underrun() ){
        __ssi_clear_underrun();
        printf("now:underrun\n");
        return (-1);
    }

    int i,j,pos,m;
    i = size / SPI_FIFO;
    j = size % SPI_FIFO;
    pos = 0;
    for(; i>0; i--)
    {
       
      //  __gpio_set_pin(3*32+19);
        for ( m = 0; m < SPI_FIFO; m ++ )
        {
            REG_SSI_DR = 0xff;
        }
        //__gpio_clear_pin(3*32+19);
       
        while( __ssi_get_rfifo_count()<SPI_FIFO ){printf("wait for rfifo\n");}
	for ( m = 0; m < SPI_FIFO; m ++ )
        {
            buf[pos++] = REG_SSI_DR;
        }

    }
    
  //  __gpio_set_pin(3*32+19);
    for(m=0;m<j;m++)
    {
        REG_SSI_DR = 0xff;
    }
   // __gpio_clear_pin(3*32+19);
    
    while( __ssi_get_rfifo_count()<j ){printf("wait rfifo\n");}
    for( ; j>0; j--)
    {
        buf[pos++] = REG_SSI_DR;
    }
    return size;    
}

int spi_write_mb_cpu(char *buf, int size)
{
    printf("spi_write_mb_cpu\n");
    if( __ssi_overrun() ){
        __ssi_clear_overrun();
        printf("now:overrun\n");
        return (-1);
    }

    int i = 0;
    //__gpio_set_pin(3*32+19);
    for(i = 0; i< size; i++)
    {
        REG_SSI_DR = buf[i];
    }
    //__gpio_clear_pin(3*32+19);
    return size;
}

void spi_sdio_init()
{
    printf("spi_sdio_init\n");
   // mdelay(1000);
    char cmd[6] = {0x40,0x00,0x00,0x00,0x00,0x95};
    char respond[6] = {0};
    int  i=0;
    for(i=0;i<10;i++)
    {   respond[0] = 0xff;
        spi_write_mb_cpu(respond,1);
    }
    spi_write_mb_cpu(cmd,6);
    //mdelay(1000);
    spi_write_mb_cpu(respond,1);
    spi_read_mb_cpu(respond,6);
    for(i = 0;i<6;i++)
    {
        printf("%d:%x\n",i,respond[i]);
    }

    cmd[0] = 0x45;
    cmd[5] = 0x01;
    spi_write_mb_cpu(cmd,6);
    mdelay(1000);
    spi_read_mb_cpu(respond,6);

    
    for(i = 0;i<6;i++)
    {
        printf("%d:%x\n",i,respond[i]);
    }
    while(1);
    cmd[0] = 5;
}

void hardware_init()
{
     ssi_init_mode_cpu();
     spi_sdio_init();
}