slcdc.c_bak

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		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_DATA | data;
		break;
	case 16:
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | (cmd&0xffff);
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_DATA | (data&0xffff);
		break;
	case 18:
		data = ((data & 0xff) << 1) | ((data & 0xff00) << 2);
		data = ((data << 6) & 0xfc0000) |((data << 4) & 0xfc00) | ((data << 2) & 0xfc);
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | (cmd&0xff00 << 2) | ((cmd & 0xff) << 1);
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_DATA | data;
		break;
	default:
		printf("Don't support %d bit Bus\n", jzfb_slcd.bus );
		break;
	}
}

/* Sent a command withou data */
void Mcupanel_Command(u16 cmd) {
	switch (jzfb_slcd.bus) {
	case 8:
	case 9:
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | ((cmd&0xff00) >> 8);
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | ((cmd&0xff) >> 0);
		break;
	case 16:
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | (cmd&0xffff);
		break;
	case 18:
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | ((cmd&0xff00) << 2) | ((cmd&0xff) << 1);
		break;
	default:
		printf("Don't support %d bit Bus\n", jzfb_slcd.bus );
		break;
	}
}

/*prepare descriptor in memory*/
static void lcd_descriptor_init(void)
{
	int i;
	unsigned int pal_size;
	unsigned int frm_size;
	struct jz_dma_desc *pal_desc, *frame_desc0, *frame_desc1;
	lcd_frame_desc2 = (struct jz_dma_desc *)LCD_UNCACHED(lcd_frame_desc2_room);
	
	pal_desc	= &lcd_palette_desc;
	frame_desc0	= &lcd_frame_desc2[0];
	frame_desc1	= &lcd_frame_desc2[0];
	
	
	i = jzfb_slcd.bpp;
	if (i == 15)
		i = 16;
	if( i == 18)
		i = 32;
	frm_size = (jzfb_slcd.w*jzfb_slcd.h*i)>>3;

	switch (jzfb_slcd.bpp) {
	case 1:
		pal_size = 4;
		break;
	case 2:
		pal_size = 8;
		break;
	case 4:
		pal_size = 32;
		break;
	case 8:
	default:
		pal_size = 512;
		break;
	}

	/* Prepare Palette Descriptor */
	pal_desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32
		| DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_16BYTE | DMAC_DCMD_TM | DMAC_DCMD_DES_V 
//		| DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE; /*refresh according event*/
		| DMAC_DCMD_DES_VIE | DMAC_DCMD_LINK; /*refresh according always*/
	switch (lcd_palette_desc.dcmd & DMAC_DCMD_DS_MASK) {
	case DMAC_DCMD_DS_32BYTE:
		pal_size /= 32;
		break;
	case DMAC_DCMD_DS_16BYTE:
		pal_size /= 16;
		break;
	case DMAC_DCMD_DS_32BIT:
		pal_size /= 4;
		break;
	case DMAC_DCMD_DS_16BIT:
		pal_size /= 2;
		break;
	case DMAC_DCMD_DS_8BIT:
	default:
		break;
	}
	pal_desc->dsadr = PHYS(jzfb_slcd.pal);    /* DMA source address */
	pal_desc->dtadr = PHYS(SLCD_FIFO);    /* DMA target address */
	pal_desc->ddadr = ((PHYS(frame_desc0) >> 4) << 24) | (pal_size & 0xffffff);    /* offset and size*/
	/*Prepare Frame Descriptor in memory*/
	switch (jzfb_slcd.bpp) {
	case 8 ... 16:
		frame_desc0->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32
			| DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE | DMAC_DCMD_TM | DMAC_DCMD_DES_V
//			| DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE; /*refresh slcd single*/
			| DMAC_DCMD_DES_VIE | DMAC_DCMD_LINK;/*refresh slcd always*/
	break;

	case 17 ... 32:
		frame_desc0->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32
			| DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE | DMAC_DCMD_TM | DMAC_DCMD_DES_V
//			| DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE; /*refresh slcd single*/
			| DMAC_DCMD_DES_VIE | DMAC_DCMD_LINK;/*refresh slcd always*/

		break;
	}
	switch (frame_desc0->dcmd & DMAC_DCMD_DS_MASK) {
	case DMAC_DCMD_DS_32BYTE:
		frm_size /= 32;
		break;
	case DMAC_DCMD_DS_16BYTE:
		frm_size /= 16;
		break;
	case DMAC_DCMD_DS_32BIT:
		frm_size /= 4;
		break;
	case DMAC_DCMD_DS_16BIT:
		frm_size /= 2;
		break;
	case DMAC_DCMD_DS_8BIT:
	default:
		break;
	}
	frame_desc0->dsadr = PHYS(jzfb_slcd.frame);   /* DMA source address */
	frame_desc0->dtadr = PHYS(SLCD_FIFO);    /* DMA target address */
	frame_desc0->ddadr = ((PHYS(frame_desc0) >> 4) << 24) | (frm_size & 0xffffff);
	dprintf("frame_desc0->dcmd = 0x%08x\n", frame_desc0->dcmd);
	dprintf("frame_desc0->dsadr = 0x%08x\n", frame_desc0->dsadr);
	dprintf("frame_desc0->dtadr = 0x%08x\n", frame_desc0->dtadr);
	dprintf("frame_desc0->ddadr = 0x%08x\n", frame_desc0->ddadr);

	/* Frame Descriptor 1 */
	for(i = 0;i < FRAMEBUF_NUM;i++)
	{
		frame_desc1->dcmd	= frame_desc0->dcmd;
		frame_desc1->dsadr	= PHYS(jzfb_slcd.frame2[i]);
		frame_desc1->dtadr	= PHYS(SLCD_FIFO);
		frame_desc1->ddadr	= ((PHYS(frame_desc1) >> 4) << 24) | (frm_size & 0xffffff);
		frame_desc1++;
	}


	if(FRAMEBUF_NUM > 1)
	{	
		old_lcd_frame_desc = &lcd_frame_desc2[1];
		//printf("old_lcd_frame_desc->buf = %x\n",old_lcd_frame_desc->buf);
	}
	cur_lcd_frame_desc = &lcd_frame_desc2[0];	
}

/* Descriptor transfer */
static int slcd_dma_init(void)
{
	/* Request DMA channel and setup irq handler */
	dma_stop(dma_chan);
	dma_request(dma_chan, slcd_dma_irq, 0, 0, DMAC_DRSR_RS_SLCD);

	/*Init the SLCD DMA and Enable*/
	REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_SLCD;
	REG_DMAC_DMACR = DMAC_DMACR_DMAE;
	REG_DMAC_DCCSR(dma_chan) =  DMAC_DCCSR_EN; /*Descriptor Transfer*/
	if (jzfb_slcd.bpp <= 8)
		REG_DMAC_DDA(dma_chan) = PHYS(&lcd_palette_desc);
	else
		REG_DMAC_DDA(dma_chan) = PHYS(&lcd_frame_desc2[0]);

	/* DMA doorbell set -- start DMA now ... */
	__dmac_channel_set_doorbell(dma_chan); /*enable this if refresh screen always*/
	return 0;
}


/*SLCD controller initialization*/
static int controller_init(void)
{
	unsigned int val, pclk;
	int pll_div;

	REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK;
	REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD;

	if ((jzfb_slcd.bpp == 18) | (jzfb_slcd.bpp == 24))
		jzfb_slcd.bpp = 32;

	/* Configure SLCD module for initialize smart lcd registers*/
	switch (jzfb_slcd.bus) {
	case 8:
		REG_SLCD_CFG = SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_8_x2 
			| SLCD_CFG_CWIDTH_8BIT | SLCD_CFG_CS_ACTIVE_LOW 
			| SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING 
			| SLCD_CFG_TYPE_PARALLEL;
		__gpio_as_slcd_8bit();
		break;
	case 9:
		REG_SLCD_CFG = SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_8_x2
			| SLCD_CFG_CWIDTH_8BIT | SLCD_CFG_CS_ACTIVE_LOW 
			| SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING 
			| SLCD_CFG_TYPE_PARALLEL;
		__gpio_as_slcd_9bit();
		break;
	case 16:
		REG_SLCD_CFG = SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_16
			| SLCD_CFG_CWIDTH_16BIT | SLCD_CFG_CS_ACTIVE_LOW
			| SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING
			| SLCD_CFG_TYPE_PARALLEL;
		__gpio_as_slcd_16bit();
		break;
	case 18:
		REG_SLCD_CFG = SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_18
			| SLCD_CFG_CWIDTH_18BIT | SLCD_CFG_CS_ACTIVE_LOW 
			| SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING 
			| SLCD_CFG_TYPE_PARALLEL;
		__gpio_as_slcd_18bit();
		break;
	default:
		printf("Error: Don't support BUS %d!\n", jzfb_slcd.bus);
		break;
	}

	REG_SLCD_CTRL = SLCD_CTRL_DMA_EN;
	__cpm_stop_lcd();
	pclk = jzfb_slcd.pclk;
	pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
	pll_div = pll_div ? 1 : 2 ;
	val = ( __cpm_get_pllout()/pll_div ) / pclk;
	val--;
	if ( val > 0x1ff ) {
		printf("CPM_LPCDR too large, set it to 0x1ff\n");
		val = 0x1ff;
	}
	__cpm_set_pixdiv(val);

	REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */

	printf("SLCDC: PixClock:%d LcdClock:%d\n",
	        __cpm_get_pixclk(), __cpm_get_lcdclk());

	__cpm_start_lcd();
	udelay(1000);
	slcd_board_init();
	/* Configure SLCD module for transfer data to smart lcd GRAM*/
	switch (jzfb_slcd.bus) {
	case 8:
		switch (jzfb_slcd.bpp) {
		case 8:
			REG_SLCD_CFG &= ~SLCD_CFG_DWIDTH_MASK;
			REG_SLCD_CFG |= SLCD_CFG_DWIDTH_8_x1;
			break;
		case 15:
		case 16:
			REG_SLCD_CFG &= ~SLCD_CFG_DWIDTH_MASK;
			REG_SLCD_CFG |= SLCD_CFG_DWIDTH_8_x2;
			break;
		case 17 ... 32:
			REG_SLCD_CFG &= ~SLCD_CFG_DWIDTH_MASK;
			REG_SLCD_CFG |= SLCD_CFG_DWIDTH_8_x3;
			break;
		default:
			printf("The BPP %d is not supported\n", jzfb_slcd.bpp);
			break;
		}
		break;
	case 9:
		switch (jzfb_slcd.bpp) {
		case 18:
			REG_SLCD_CFG &= ~SLCD_CFG_DWIDTH_MASK;
			REG_SLCD_CFG |= SLCD_CFG_DWIDTH_9_x2;
			break;
		default:
			printf("The BPP %d is not supported\n", jzfb_slcd.bpp);
			break;
		}
		break;
	case 16:
		switch (jzfb_slcd.bpp) {
		case 15 ... 16:
			REG_SLCD_CFG &= ~SLCD_CFG_DWIDTH_MASK;
			REG_SLCD_CFG |= SLCD_CFG_DWIDTH_16;
			break;
		case 17 ... 32:
			REG_SLCD_CFG &= ~SLCD_CFG_DWIDTH_MASK;
			REG_SLCD_CFG |= SLCD_CFG_DWIDTH_9_x2;
//			REG_SLCD_CFG |= SLCD_CFG_DWIDTH_16;
			break;
		default:
			printf("The BPP %d is not supported\n", jzfb_slcd.bpp);
			break;
		}
		break;
	case 18:
		switch (jzfb_slcd.bpp) {
		case 17 ... 32:
			REG_SLCD_CFG &= ~SLCD_CFG_DWIDTH_MASK;
			REG_SLCD_CFG |= SLCD_CFG_DWIDTH_18;
			break;
		default:
			printf("The BPP %d is not supported\n", jzfb_slcd.bpp);
			jzfb_slcd.bpp = 18;
			break;
		}
		break;
	default:
		printf("Error: The BUS %d is not supported\n", jzfb_slcd.bus);
		break;
	}
	dprintf("SLCD_CFG=0x%x\n", REG_SLCD_CFG);
	return 0;
}


void testlcd(void)
{
	u32 *buf;
	int i, j;
	buf = (u32 *)lcd_get_cframe();
	for(i = 0; i<320; i++)
		for(j = 0; j<240; j++)
			*(buf+i*240+j) = 0;
}

/*The initialization of smart lcd*/
int jzlcd_init(void)
{
	int err = 0;
	printf("SLCD Init!\n");

	err = fb_malloc();
	if (err) 
		goto failed;
	printf("fb_malloc \n");
	err = controller_init();
	printf("controller_init \n");
	if (err)
		goto failed;

	lcd_descriptor_init();
	printf("lcd_descriptor_init \n");
	__dcache_writeback_all();
	err = slcd_dma_init();
	printf("slcd_dma_init \n");
	if (err)
		goto failed;
	__slcd_set_backlight_level(80);
//	testlcd();
//	printf("testlcd \n");
//	while(1)
//#error oifdsj[ifdjsjjjjj
	return 0;

failed:
	return err;

}

#if (DM==1)
int  lcd_poweron(void)
{
}
int  lcd_poweroff(void)
{
}
int lcd_preconvert(void)
{
//	__cpm_stop_lcd();

	return 1;
}
int  lcd_convert(void)
{

}
void  mng_init_lcd(void)
{
	struct dm_jz4740_t lcd_dm;
	lcd_dm.name = "SLCD driver";	
	lcd_dm.init = jzlcd_init;  
	lcd_dm.poweron = lcd_poweron;
	lcd_dm.poweroff = lcd_poweroff;
	lcd_dm.convert = lcd_convert;
	lcd_dm.preconvert = lcd_preconvert;
	dm_register(0,&lcd_dm);
}
void lcdstop()
{
	__slcd_close_backlight();
	__dmac_disable_channel(dma_chan);
	__slcd_dma_disable(); 
	__slcd_special_off(); 
	__cpm_stop_lcd();

}
void lcdstart()
{
	controller_init();
	__slcd_set_backlight_level(80);
}
#endif