lgdp4551.c

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/*
 * jz4740/drv/slcd/spfd5420a.c -- Ingenic On-Chip SLCD frame buffer device
 *
 * Copyright (C) 2005-2007, Ingenic Semiconductor Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#if SLCDTYPE == 101 || SLCDTYPE == 102

#if SLCDTYPE == 101
#define HTW_SLCD_TYPE 0x1098
#elif SLCDTYPE == 102
#define HTW_SLCD_TYPE 0x10a8
#endif

#include <jz4740.h>
#ifndef __SLCDC_H__
#define __SLCDC_H__

#define STFT_PSHI	(1 << 15)
#define STFT_CLSHI	(1 << 14)
#define STFT_SPLHI	(1 << 13)
#define STFT_REVHI	(1 << 12)

#define SYNC_MASTER	(0 << 16)
#define SYNC_SLAVE	(1 << 16)

#define DE_P		(0 << 9)
#define DE_N		(1 << 9)

#define PCLK_P		(0 << 10)
#define PCLK_N		(1 << 10)

#define HSYNC_P		(0 << 11)
#define HSYNC_N		(1 << 11)

#define VSYNC_P		(0 << 8)
#define VSYNC_N		(1 << 8)

#define DATA_NORMAL	(0 << 17)
#define DATA_INVERSE	(1 << 17)

#define MODE_MASK		0x0f
#define MODE_TFT_18BIT		(1 << 7)
#define MODE_8BIT_SERIAL_TFT    0x0c
#define MODE_TFT_GEN		0x00
#define MODE_TFT_SHARP		0x01
#define MODE_TFT_CASIO		0x02
#define MODE_TFT_SAMSUNG	0x03
#define MODE_CCIR656_NONINT	0x04
#define MODE_CCIR656_INT	0x05
#define MODE_STN_COLOR_SINGLE	0x08
#define MODE_STN_MONO_SINGLE	0x09
#define MODE_STN_COLOR_DUAL	0x0a
#define MODE_STN_MONO_DUAL	0x0b

#define STN_DAT_PIN1	(0x00 << 4)
#define STN_DAT_PIN2	(0x01 << 4)
#define STN_DAT_PIN4	(0x02 << 4)
#define STN_DAT_PIN8	(0x03 << 4)
#define STN_DAT_PINMASK	STN_DAT_PIN8

#ifndef u8
#define u8	unsigned char
#endif

#ifndef u16
#define u16	unsigned short
#endif

#ifndef u32
#define u32	unsigned int
#endif

#ifndef NULL
#define NULL	0
#endif

#define NR_PALETTE	256

struct jz_dma_desc {
	 u32 dcmd;	/* DCMD value for the current transfer */
	 u32 dsadr;	/* DSAR value for the current transfer */
	 u32 dtadr;	/* DTAR value for the current transfer */
	 u32 ddadr;	/* Points to the next descriptor + transfer count */
};

#define  FRAMEBUF_NUM 3

struct jzfb_slcd_info {

	u32 cfg;	/* panel mode and pin usage etc. */
	u32 w;
	u32 h;
	u32 bpp;	/* bit per pixel */
	u32 bus;
	u32 pclk;	/* frame clk */

	u8 *cpal;	/* Cacheable Palette Buffer */
	u8 *pal;	/* Non-cacheable Palette Buffer */
	u8 *cframe;	/* Cacheable Frame Buffer */
	u8 *frame;	/* Non-cacheable Frame Buffer */
	u8 *cframe2[FRAMEBUF_NUM];	/* Cacheable Frame Buffer */
	u8 *frame2[FRAMEBUF_NUM];	  /* Non-cacheable Frame Buffer */

	struct {
		u8 red, green, blue;
	} palette[NR_PALETTE];
};

extern struct jzfb_slcd_info jzfb_slcd;

//extern void Mcupanel_RegSet(u32 cmd, u32 data);
//extern void Mcupanel_Command(u32 cmd);

#undef LCD_UNCACHED
#define LCD_UNCACHED(addr)	((unsigned int)(addr) | 0xa0000000)


int jzlcd_init(void);

#endif /* __LCDC_H__ */


//#define PIN_CS_N 	(32*2+18)	/* Chip select | GPC18 */
#define PIN_CS_N 	(32*2+22)	/* Chip select | GPC22;*/
#define PIN_RESET_N 	(32*1+18)	/* LCD reset   | GPB18 */
#define PIN_RS_N 	(32*2+19)	/* LCD RS      | GPC19 */
#define PIN_POWER_N	(32*3+28)	/* Power off   | GPD0  */
#define PIN_FMARK_N	(32*3+1)	/* fmark       | GPD1  */

unsigned int stat = 0;


#if SLCDTYPE == 101
extern void Mcupanel_RegSet(u32 cmd, u32 data);
extern void Mcupanel_Command(u32 cmd);
#elif SLCDTYPE == 102
static void Mcupanel_RegSet(unsigned int cmd, unsigned int data)
{
	switch (jzfb_slcd.bus) {
	case 8:
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | ((cmd&0xff00) >> 8);
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | ((cmd&0xff) >> 0);
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_DATA | (data&0xffff);
		break;
	case 9:
		data = ((data & 0xff) << 1) | ((data & 0xff00) << 2);
		data = ((data << 6) & 0xfc0000) | ((data << 4) & 0xfc00) | ((data << 2) & 0xfc);
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | ((cmd&0xff00) >> 8);
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | ((cmd&0xff) >> 0);
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_DATA | data;
		break;
	case 16:
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | (cmd&0xffff);
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_DATA | (data&0xffff);
		break;
	case 18: 
		//cmd = ((cmd & 0xff) << 1) | ((cmd & 0xff00) << 2); 
		cmd = (((cmd&0xfff)<<1) | ((cmd&0xf000)<<2));
 		//data = ((data & 0xff) << 1) | ((data & 0xff00) << 2);
 		data = (((data&0xfff)<<1) | ((data&0xf000)<<2));
 		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | cmd;
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_DATA | ((data<<6)&0xfc0000)|((data<<4)&0xfc00) | ((data<<2)&0xfc);
		break;
	default:
		printf("Don't support %d bit Bus\n", jzfb_slcd.bus );
		break;
	}
}

/* Sent a command without data */
static void Mcupanel_Command(unsigned int cmd) {
	switch (jzfb_slcd.bus) {
	case 8:
	case 9:
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | ((cmd&0xff00) >> 8);
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | ((cmd&0xff) >> 0);
		break;
	case 16:
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | (((cmd&0xff)<<1) | ((cmd&0xff00)<<2));
		break;
	case 18:
		while (REG_SLCD_STATE & SLCD_STATE_BUSY);
		REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | ((cmd&0xf000) << 2) | ((cmd&0xfff) << 1);
		break;
	default:
		printf("Don't support %d bit Bus\n", jzfb_slcd.bus );
		break;
	}
}

#endif

/* Set the start address of screen, for example (0, 0) */
void Mcupanel_SetAddr(u32 x, u32 y) //u32
{
	//Mcupanel_RegSet(0x200,x) ;
	Mcupanel_RegSet(0x20,x) ;
	udelay(1);
	//Mcupanel_RegSet(0x201,y) ;
	Mcupanel_RegSet(0x21,y) ;
	udelay(1);
	//Mcupanel_Command(0x202);
	Mcupanel_Command(0x22);

}

static void __slcd_special_pin_init(void)
{
	//__gpio_as_output(PIN_CS_N);
	__gpio_as_output(PIN_RESET_N);
	//__gpio_clear_pin(PIN_CS_N); /* Clear CS */	
	//__gpio_as_output(PIN_POWER_N);
	
	mdelay(100);
}

static void detect_fmark_status(void *arg)
{

	unsigned int gpio_state = 0;
	unsigned int count = 0;
	static unsigned int i;
	u8 byte1 , byte2 ,err;
	
	enum {
			FMARK_RISE,
			FMARK_FALL,
		}stat;
	
	gpio_state = __gpio_get_pin(PIN_FMARK_N);
	
	while(1)
	{
		udelay(1);
		if(gpio_state == __gpio_get_pin(PIN_FMARK_N))
		{
			count++;
			if(count > 2000)
				break;
		}else
		{
			count = 0;
			gpio_state = __gpio_get_pin(PIN_FMARK_N);
		}
		
	}
	
	if (gpio_state == 0)
	{
		__gpio_as_irq_rise_edge(PIN_FMARK_N);
		stat = FMARK_RISE; // here is rise edge
	}
	else if (gpio_state == 1)
	{
		__gpio_as_irq_fall_edge(PIN_FMARK_N);	// here is fall edge
		stat = FMARK_FALL;
	}	
}

static int GAMMA()
{
    
	Mcupanel_RegSet(0x0300,0x0101);
	Mcupanel_RegSet(0x0301,0x0b27);
	Mcupanel_RegSet(0x0302,0x132a);
	Mcupanel_RegSet(0x0303,0x2a13);
	Mcupanel_RegSet(0x0304,0x270b);
	Mcupanel_RegSet(0x0305,0x0101);
	Mcupanel_RegSet(0x0306,0x1205);
	Mcupanel_RegSet(0x0307,0x0512);
	Mcupanel_RegSet(0x0308,0x0005);
	Mcupanel_RegSet(0x0309,0x0003);
	Mcupanel_RegSet(0x030a,0x0f04);
	Mcupanel_RegSet(0x030b,0x0f00);
	Mcupanel_RegSet(0x030c,0x000f);
	Mcupanel_RegSet(0x030d,0x040f);
	Mcupanel_RegSet(0x030e,0x0300);
	Mcupanel_RegSet(0x030f,0x0500);
	//**************secorrect gamma2 *********
	Mcupanel_RegSet(0x0400,0x3500);
	Mcupanel_RegSet(0x0401,0x0001);
	Mcupanel_RegSet(0x0404,0x0000);
	
	Mcupanel_RegSet(0x0500,0x0000);
	Mcupanel_RegSet(0x0501,0x0000);
	Mcupanel_RegSet(0x0502,0x0000);
	Mcupanel_RegSet(0x0503,0x0000);      //
	Mcupanel_RegSet(0x0504,0x0000);      //
	Mcupanel_RegSet(0x0505,0x0000);

	Mcupanel_RegSet(0x0600,0x0000);
	Mcupanel_RegSet(0x0606,0x0000);
	Mcupanel_RegSet(0x06f0,0x0000);
	
	Mcupanel_RegSet(0x07f0,0x5420);      //
	Mcupanel_RegSet(0x07f3,0x288a);      //
	Mcupanel_RegSet(0x07f4,0x0022);      //
	Mcupanel_RegSet(0x07f5,0x0001);      //
	Mcupanel_RegSet(0x07f0,0x0000);      //

}

#define W_Reg_Data Mcupanel_RegSet
#define delay50ms()  mdelay(50)
/*************************************************
		 初始化程序5408--KGM281J--0802
*************************************************/
static void initial()
{
	/*RESETB = 1;
	delay50ms();
	RESETB = 0;
	delay50ms();
	RESETB = 1;
	delay50ms();
	*/
	
	W_Reg_Data(0x0000, 0x0000);		// Start internal OSC.
	W_Reg_Data(0x0001, 0x0000);		// set SS and SM bit
	W_Reg_Data(0x0002, 0x05ff);		// set Frame inversion
	W_Reg_Data(0x0003, 0X1098/*HTW_SLCD_TYPE*/);		// set GRAM write direction and BGR=1.
	W_Reg_Data(0x0004, 0x0000);		// Resize register
	W_Reg_Data(0x0008, 0x0207);		// set the back porch and front porch
	W_Reg_Data(0x0009, 0x0000);		// set non-display area refresh cycle ISC[3:0]
	W_Reg_Data(0x000A, 0x0000);		// FMARK function
	W_Reg_Data(0x000C, 0x0000);		// RGB interface setting
	W_Reg_Data(0x000D, 0x0000);		// Frame marker Position
	W_Reg_Data(0x000F, 0x0000);		// RGB interface polarity

	W_Reg_Data(0x0007, 0x0101);
	W_Reg_Data(0x0010, 0x12B0);		// SAP, BT[3:0], AP, DSTB, SLP, STB
	W_Reg_Data(0x0011, 0x0007);		// DC1[2:0], DC0[2:0], VC[2:0]
	delay50ms();
	W_Reg_Data(0x0007, 0x0001);
	W_Reg_Data(0x0012, 0x01bb);		// VREG1OUT voltage
	delay50ms();
	W_Reg_Data(0x0013, 0x1D00);		// VDV[4:0] for VCOM amplitude
	W_Reg_Data(0x0029, 0x000A);		// VCM[4:0] for VCOMH
	delay50ms();					// Delay 50ms

	W_Reg_Data(0x0030, 0x0102);
	W_Reg_Data(0x0031, 0x0C15);
	W_Reg_Data(0x0032, 0x0B18);
	W_Reg_Data(0x0033, 0x1C0F);
	W_Reg_Data(0x0034, 0x120B);
	W_Reg_Data(0x0035, 0x0A04);
	W_Reg_Data(0x0036, 0x1F00);
	W_Reg_Data(0x0037, 0x051F);
	W_Reg_Data(0x0038, 0x0305);
	W_Reg_Data(0x0039, 0x0A05);