ethif_cs8900_jz4740_poll.c

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/* Jz ethernet support
 *
 *  Copyright (c) 2005
 *  Ingenic Semiconductor, <[e-mail]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* ********************************************************************* */

#include "jz4740.h"
#include "jz_cs8900.h"
#include "ethif_cs8900_jz4740.h"

#include "lwip/debug.h"
#include "lwip/opt.h"
#include "lwip/def.h"
#include "lwip/mem.h"
#include "lwip/pbuf.h"
#include "lwip/stats.h"
#include "lwip/sys.h"
#include "netif/etharp.h"

/* ********************************************************************* */
/* File local definitions */

/* Define those to better describe your network interface. */
//#define Print_Header
#define IFNAME0 'e'
#define IFNAME1 'n'

/* ********************************************************************* */
#define PKTSIZE_ALIGN 2048
#define PKTALIGN      32
#define PKTBUFSRX     16
#define MIN_PACKET_SIZE 60
static int next_rx;
static int next_tx;

volatile u8_t  PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN] __attribute__ ((aligned (PKTSIZE_ALIGN)));
volatile u8_t *NetTxPacket = 0; 
volatile u8_t *NetRxPackets[PKTBUFSRX];

/* packet page register access functions */

#ifdef CS8900_BUS32
/* we don't need 16 bit initialisation on 32 bit bus */
#define get_reg_init_bus(x) get_reg((x))
#else
static unsigned short get_reg_init_bus (int regno)
{
	/* force 16 bit busmode */
	volatile unsigned char c;
    //c = CS8900_BUS16_0;
	//c = CS8900_BUS16_1;
	//c = CS8900_BUS16_0;
	//c = CS8900_BUS16_1;
	//c = CS8900_BUS16_0;

	CS8900_PPTR = regno;
//	printf("CS8900_PPTR:%08x\n",&CS8900_PPTR);
    udelay(100);
	
	return (unsigned short) CS8900_PDATA;
}
#endif

//MAC 
#define ETHADDR0 0x00 
#define ETHADDR1 0x01 
#define ETHADDR2 0x02 
#define ETHADDR3 0x03 
#define ETHADDR4 0x04 
#define ETHADDR5 0x06 

/////////////***************get timer******************/////////////////////////////

#define TIMER_CHAN  0
#define TIMER_FDATA 0xffff  /* Timer full data value */
#define TIMER_HZ    (CFG_HZ/4)
static ulong timestamp;
static ulong lastdec;
#define READ_TIMER  REG_TCU_TCNT(TIMER_CHAN)  /* macro to read the 16 bit timer */

ulong get_timer(ulong base)
{
	return get_timer_masked () - base;
}

ulong get_timer_masked (void)
{
	ulong now = READ_TIMER;

	if (lastdec <= now) {
		/* normal mode */
		timestamp += (now - lastdec);
	} else {
		/* we have an overflow ... */
		timestamp += TIMER_FDATA + now - lastdec;
	}
	lastdec = now;

	return timestamp;
}

/////////////////////////////////////////////

static unsigned short get_reg (int regno)
{
	CS8900_PPTR = regno;
	return (unsigned short) CS8900_PDATA;
}


static void put_reg (int regno, unsigned short val)
{
	CS8900_PPTR = regno;
	CS8900_PDATA = val;
}

static void eth_reset (void)
{
	int tmo,i;
	unsigned short us;

	/* reset NIC */
	put_reg (PP_SelfCTL, get_reg (PP_SelfCTL) | PP_SelfCTL_Reset);

	/* wait for 200ms */
	for (i=0; i<200; i++) {
		udelay (1000);
	}
	/* Wait until the chip is reset */

	tmo = get_timer (0) + 1 * CFG_HZ;
	while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0)
		   && tmo < get_timer (0))
		/*NOP*/;
}

static void eth_reginit (void)
{
#if 1
	/* receive only error free packets addressed to this card */
	put_reg (PP_RxCTL, 0x0D05);
	/* do not generate any interrupts on receive operations */
	put_reg (PP_RxCFG, 0x0003);
	/* do not generate any interrupts on transmit operations */
	put_reg (PP_TxCFG, 0x0007);
	/* do not generate any interrupts on buffer operations */
	put_reg (PP_BufCFG, 0x000B);
	/* enable transmitter/receiver mode */
	put_reg (PP_LineCTL, 0x00D3);

	put_reg (0x0114, 0x0015); /* Self control     REG 15 */
	put_reg (0x0116, 0x0017);    /* Bus Control     REG 17 */
//	put_reg (0x0118, 0x0099); /* Test Control */
	put_reg (0x0150, 0x0000);/* Address Filter Register */

#endif
#if 0
	/* receive only error free packets addressed to this card */
	put_reg (PP_RxCTL, PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
	/* do not generate any interrupts on receive operations */
	put_reg (PP_RxCFG, 0);
	/* do not generate any interrupts on transmit operations */
	put_reg (PP_TxCFG, 0);
	/* do not generate any interrupts on buffer operations */
	put_reg (PP_BufCFG, 0);
	/* enable transmitter/receiver mode */
	put_reg (PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
#endif


}

static void cs8900_get_enetaddr (unsigned char * addr)
{
	int i;
	unsigned char env_enetaddr[6];
	char *tmp = getenv ("ethaddr");
	char *end;

	for (i=0; i<6; i++) {
//		env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
		if (tmp)
			tmp = (*end) ? end+1 : end;
	}

	/* verify chip id */
	if (get_reg_init_bus (PP_ChipID) != 0x630e)
		return;
	eth_reset ();
	if ((get_reg (PP_SelfST) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
			(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {

		/* Load the MAC from EEPROM */
		for (i = 0; i < 6 / 2; i++) {
			unsigned int Addr;

			Addr = get_reg (PP_IA + i * 2);
			addr[i * 2] = Addr & 0xFF;
			addr[i * 2 + 1] = Addr >> 8;
		}

		if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
		    memcmp(env_enetaddr, addr, 6) != 0) {
			printf ("\nWarning: MAC addresses don't match:\n");
			printf ("\tHW MAC address:  "
				"%02X:%02X:%02X:%02X:%02X:%02X\n",
				addr[0], addr[1],
				addr[2], addr[3],
				addr[4], addr[5] );
			printf ("\t\"ethaddr\" value: "
				"%02X:%02X:%02X:%02X:%02X:%02X\n",
				env_enetaddr[0], env_enetaddr[1],
				env_enetaddr[2], env_enetaddr[3],
				env_enetaddr[4], env_enetaddr[5]) ;
//				debug ("### Set MAC addr from environment\n");
			memcpy (addr, env_enetaddr, 6);
		}
		if (!tmp) {
			char ethaddr[20];
			sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
				 addr[0], addr[1],
				 addr[2], addr[3],
				 addr[4], addr[5]) ;
//			debug ("### Set environment from HW MAC addr = \"%s\"\n",				ethaddr);
//			setenv ("ethaddr", ethaddr);
		}

	}
}

static void jz_eth_halt (struct eth_device *dev)
{
	/* disable transmitter/receiver mode */
	put_reg (PP_LineCTL, 0);

	/* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
	get_reg_init_bus (PP_ChipID);
}

static int low_level_init(struct netif *netif)
{
	u16 id;
	int i;
#define bi_enetaddr netif->hwaddr

	/*Setup packet buffers, aligned correctly.    //net.c */
	NetTxPacket = &PktBuf[0];
	//NetTxPacket -= (ulong)NetTxPacket % PKTALIGN;
	for (i = 0; i < PKTBUFSRX; i++) {
		NetRxPackets[i] = NetTxPacket + (i+1)*PKTSIZE_ALIGN;
	}
    
	
	/* verify chip id */
	id = get_reg_init_bus (PP_ChipID);
//	printf("id:%08x PP_chipID:%08x --%08x--%08x\n",id,PP_ChipID,CS8900_BASE,&CS8900_BUS16_1);
	if (id != 0x630e) {
		printf ("CS8900 jz_eth_init error!\n");
		return 0;
	}

	eth_reset ();
	/* set the ethernet address */
	put_reg (PP_IA + 0, bi_enetaddr[0] | (bi_enetaddr[1] << 8));
	put_reg (PP_IA + 2, bi_enetaddr[2] | (bi_enetaddr[3] << 8));
	put_reg (PP_IA + 4, bi_enetaddr[4] | (bi_enetaddr[5] << 8));

	eth_reginit ();
	return 0;
}

/* Get a data block via Ethernet */
//static int jz_eth_rx (struct eth_device* dev)
static struct pbuf *ETH_Input(struct netif *netif)
{
	struct pbuf *p = NULL, *q = NULL;
	u16 *ptr;
        int i;
	unsigned short rxlen;
	unsigned short *addr;
	unsigned short status;

	status = get_reg (PP_RER);

	if ((status & PP_RER_RxOK) == 0)
		return 0;
	status = CS8900_RTDATA;		/* stat */
	rxlen = CS8900_RTDATA;		/* len */