key_scan.csf.qmsg

此程序实现的是矩阵式键盘的扫描的电路

{ "Warning" "WTDB_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITDB_RIPPLE_CLK" "dat\[0\] " "Info: Detected ripple clock dat\[0\] as buffer" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "dat\[0\]" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "dat\[3\] " "Info: Detected ripple clock dat\[3\] as buffer" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "dat\[3\]" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "dat\[1\] " "Info: Detected ripple clock dat\[1\] as buffer" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "dat\[1\]" } } } }  } 0} { "Info" "ITDB_GATED_CLK" "i94~20 " "Info: Detected gated clock i94~20 as buffer" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 79 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "i94~20" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cnt\[1\] sta\[1\] 125.0 MHz Internal " "Info: Clock clk Internal fmax is restricted to 125.0 MHz between source register cnt\[1\] and destination register sta\[1\]" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register register " "Info: + Longest register to register delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[1\] 1 REG LC2_A6 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A6; Fanout = 6; REG Node = 'cnt\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { cnt[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.900 ns) 1.500 ns sta\[1\] 2 REG LC6_A6 1 " "Info: 2: + IC(0.600 ns) + CELL(0.900 ns) = 1.500 ns; Loc. = LC6_A6; Fanout = 1; REG Node = 'sta\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "1.500 ns" { cnt[1] sta[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns 60.00 % " "Info: Total cell delay = 0.900 ns ( 60.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 40.00 % " "Info: Total interconnect delay = 0.600 ns ( 40.00 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "1.500 ns" { cnt[1] sta[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 14 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns sta\[1\] 2 REG LC6_A6 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC6_A6; Fanout = 1; REG Node = 'sta\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.000 ns" { clk sta[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk sta[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 14 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns cnt\[1\] 2 REG LC2_A6 6 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_A6; Fanout = 6; REG Node = 'cnt\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.000 ns" { clk cnt[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk cnt[1] } "NODE_NAME" } } }  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk sta[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk cnt[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 26 -1 0 } }  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "1.500 ns" { cnt[1] sta[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk sta[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk cnt[1] } "NODE_NAME" } } }  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { sta[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 26 -1 0 } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 4 " "Warning: Circuit may not operate. Detected 4 non-operational path(s) clocked by clock clk with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "seg7\[1\] seg7_out\[1\]~reg0 clk 7.0 ns " "Info: Found hold time violation between source pin or register seg7\[1\] and destination pin or register seg7_out\[1\]~reg0 for clock clk (Hold time is 7.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "8.000 ns + Largest " "Info: + Largest clock skew is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.900 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 11.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 14 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns dat\[1\] 2 REG LC2_C3 1 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC2_C3; Fanout = 1; REG Node = 'dat\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.900 ns" { clk dat[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 7.300 ns i94~20 3 COMB LC1_C3 4 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 7.300 ns; Loc. = LC1_C3; Fanout = 4; COMB Node = 'i94~20'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.500 ns" { dat[1] i94~20 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 79 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.900 ns seg7_out\[1\]~reg0 4 REG LC7_C12 1 " "Info: 4: + IC(4.600 ns) + CELL(0.000 ns) = 11.900 ns; Loc. = LC7_C12; Fanout = 1; REG Node = 'seg7_out\[1\]~reg0'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "4.600 ns" { i94~20 seg7_out[1]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.700 ns 39.50 % " "Info: Total cell delay = 4.700 ns ( 39.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns 60.50 % " "Info: Total interconnect delay = 7.200 ns ( 60.50 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "11.900 ns" { clk dat[1] i94~20 seg7_out[1]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns - Shortest register " "Info: - Shortest clock path from clock clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 14 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns seg7\[1\] 2 REG LC4_C12 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC4_C12; Fanout = 1; REG Node = 'seg7\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.000 ns" { clk seg7[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk seg7[1] } "NODE_NAME" } } }  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "11.900 ns" { clk dat[1] i94~20 seg7_out[1]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk seg7[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns - " "Info: - Micro clock to output delay of source is 0.900 ns" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns - Shortest register register " "Info: - Shortest register to register delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seg7\[1\] 1 REG LC4_C12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C12; Fanout = 1; REG Node = 'seg7\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { seg7[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.900 ns) 1.500 ns seg7_out\[1\]~reg0 2 REG LC7_C12 1 " "Info: 2: + IC(0.600 ns) + CELL(0.900 ns) = 1.500 ns; Loc. = LC7_C12; Fanout = 1; REG Node = 'seg7_out\[1\]~reg0'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "1.500 ns" { seg7[1] seg7_out[1]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns 60.00 % " "Info: Total cell delay = 0.900 ns ( 60.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 40.00 % " "Info: Total interconnect delay = 0.600 ns ( 40.00 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "1.500 ns" { seg7[1] seg7_out[1]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 84 -1 0 } }  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "11.900 ns" { clk dat[1] i94~20 seg7_out[1]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk seg7[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "1.500 ns" { seg7[1] seg7_out[1]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "seg7\[2\] kbcol\[3\] clk 11.700 ns register " "Info: tsu for register seg7\[2\] (data pin = kbcol\[3\], clock pin = clk) is 11.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.300 ns + Longest pin register " "Info: + Longest pin to register delay is 14.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns kbcol\[3\] 1 PIN Pin_25 5 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_25; Fanout = 5; PIN Node = 'kbcol\[3\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { kbcol[3] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.700 ns) + CELL(1.400 ns) 10.200 ns i~43 2 COMB LC3_C12 3 " "Info: 2: + IC(5.700 ns) + CELL(1.400 ns) = 10.200 ns; Loc. = LC3_C12; Fanout = 3; COMB Node = 'i~43'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "7.100 ns" { kbcol[3] i~43 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.400 ns) 14.300 ns seg7\[2\] 3 REG LC3_A6 1 " "Info: 3: + IC(2.700 ns) + CELL(1.400 ns) = 14.300 ns; Loc. = LC3_A6; Fanout = 1; REG Node = 'seg7\[2\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "4.100 ns" { i~43 seg7[2] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.900 ns 41.26 % " "Info: Total cell delay = 5.900 ns ( 41.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.400 ns 58.74 % " "Info: Total interconnect delay = 8.400 ns ( 58.74 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "14.300 ns" { kbcol[3] i~43 seg7[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 14 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns seg7\[2\] 2 REG LC3_A6 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_A6; Fanout = 1; REG Node = 'seg7\[2\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.000 ns" { clk seg7[2] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk seg7[2] } "NODE_NAME" } } }  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "14.300 ns" { kbcol[3] i~43 seg7[2] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk seg7[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg7_out\[0\] seg7_out\[0\]~reg0 18.900 ns register " "Info: tco from clock clk to destination pin seg7_out\[0\] through register seg7_out\[0\]~reg0 is 18.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.900 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 11.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 14 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns dat\[1\] 2 REG LC2_C3 1 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC2_C3; Fanout = 1; REG Node = 'dat\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.900 ns" { clk dat[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 7.300 ns i94~20 3 COMB LC1_C3 4 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 7.300 ns; Loc. = LC1_C3; Fanout = 4; COMB Node = 'i94~20'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.500 ns" { dat[1] i94~20 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 79 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.900 ns seg7_out\[0\]~reg0 4 REG LC5_C12 1 " "Info: 4: + IC(4.600 ns) + CELL(0.000 ns) = 11.900 ns; Loc. = LC5_C12; Fanout = 1; REG Node = 'seg7_out\[0\]~reg0'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "4.600 ns" { i94~20 seg7_out[0]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.700 ns 39.50 % " "Info: Total cell delay = 4.700 ns ( 39.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns 60.50 % " "Info: Total interconnect delay = 7.200 ns ( 60.50 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "11.900 ns" { clk dat[1] i94~20 seg7_out[0]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 84 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest register pin " "Info: + Longest register to pin delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seg7_out\[0\]~reg0 1 REG LC5_C12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C12; Fanout = 1; REG Node = 'seg7_out\[0\]~reg0'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { seg7_out[0]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 84 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(3.900 ns) 6.100 ns seg7_out\[0\] 2 PIN Pin_59 0 " "Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = Pin_59; Fanout = 0; PIN Node = 'seg7_out\[0\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "6.100 ns" { seg7_out[0]~reg0 seg7_out[0] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 63.93 % " "Info: Total cell delay = 3.900 ns ( 63.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 36.07 % " "Info: Total interconnect delay = 2.200 ns ( 36.07 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "6.100 ns" { seg7_out[0]~reg0 seg7_out[0] } "NODE_NAME" } } }  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "11.900 ns" { clk dat[1] i94~20 seg7_out[0]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "6.100 ns" { seg7_out[0]~reg0 seg7_out[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "seg7\[1\] kbcol\[2\] clk -1.700 ns register " "Info: th for register seg7\[1\] (data pin = kbcol\[2\], clock pin = clk) is -1.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 14 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns seg7\[1\] 2 REG LC4_C12 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC4_C12; Fanout = 1; REG Node = 'seg7\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.000 ns" { clk seg7[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk seg7[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns kbcol\[2\] 1 PIN Pin_27 5 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_27; Fanout = 5; PIN Node = 'kbcol\[2\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { kbcol[2] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.400 ns) 7.000 ns seg7\[1\] 2 REG LC4_C12 1 " "Info: 2: + IC(2.500 ns) + CELL(1.400 ns) = 7.000 ns; Loc. = LC4_C12; Fanout = 1; REG Node = 'seg7\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { kbcol[2] seg7[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 64.29 % " "Info: Total cell delay = 4.500 ns ( 64.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 35.71 % " "Info: Total interconnect delay = 2.500 ns ( 35.71 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "7.000 ns" { kbcol[2] seg7[1] } "NODE_NAME" } } }  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk seg7[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "7.000 ns" { kbcol[2] seg7[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk kbrow\[3\] kbrow\[3\]~reg0 9.600 ns register " "Info: Minimum tco from clock clk to destination pin kbrow\[3\] through register kbrow\[3\]~reg0 is 9.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 14 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns kbrow\[3\]~reg0 2 REG LC1_A9 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'kbrow\[3\]~reg0'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.000 ns" { clk kbrow[3]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk kbrow[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns kbrow\[3\]~reg0 1 REG LC1_A9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'kbrow\[3\]~reg0'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { kbrow[3]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(3.900 ns) 4.800 ns kbrow\[3\] 2 PIN Pin_37 0 " "Info: 2: + IC(0.900 ns) + CELL(3.900 ns) = 4.800 ns; Loc. = Pin_37; Fanout = 0; PIN Node = 'kbrow\[3\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "4.800 ns" { kbrow[3]~reg0 kbrow[3] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 81.25 % " "Info: Total cell delay = 3.900 ns ( 81.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns 18.75 % " "Info: Total interconnect delay = 0.900 ns ( 18.75 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "4.800 ns" { kbrow[3]~reg0 kbrow[3] } "NODE_NAME" } } }  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk kbrow[3]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "4.800 ns" { kbrow[3]~reg0 kbrow[3] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 27 16:24:36 2008 " "Info: Processing ended: Thu Nov 27 16:24:36 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 10 s " "Info: Quartus II Full Compilation was successful. 0 errors, 10 warnings" {  } {  } 0}