key_scan.csf.qmsg

此程序实现的是矩阵式键盘的扫描的电路

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 27 16:24:11 2008 " "Info: Processing started: Thu Nov 27 16:24:11 2008" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off key_scan -c key_scan " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off key_scan -c key_scan" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_scan.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file key_scan.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 key_scan-one " "Info: Found design unit 1: key_scan-one" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "key_scan-one" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 key_scan " "Info: Found entity 1: key_scan" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "key_scan" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "key_scan.vhd(74) " "Info: VHDL Case Statement information at key_scan.vhd(74): OTHERS choice is never selected" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 74 0 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "sta\[0\] cnt\[0\] " "Info: Duplicate register sta\[0\] merged to single register cnt\[0\], power-up level changed" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 26 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dat\[2\] dat\[3\] " "Info: Duplicate register dat\[2\] merged to single register dat\[3\]" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "36 " "Info: Implemented 36 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "22 " "Info: Implemented 22 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 27 16:24:16 2008 " "Info: Processing ended: Thu Nov 27 16:24:16 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 27 16:24:21 2008 " "Info: Processing started: Thu Nov 27 16:24:21 2008" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off key_scan -c key_scan " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off key_scan -c key_scan" {  } {  } 0}