key_scan.tan.qmsg

此程序实现的是矩阵式键盘的扫描的电路

{ "Info" "ITDB_TH_RESULT" "seg7\[1\] kbcol\[2\] clk -1.700 ns register " "Info: th for register seg7\[1\] (data pin = kbcol\[2\], clock pin = clk) is -1.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 14 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns seg7\[1\] 2 REG LC4_C12 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC4_C12; Fanout = 1; REG Node = 'seg7\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.000 ns" { clk seg7[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk seg7[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns kbcol\[2\] 1 PIN Pin_27 5 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_27; Fanout = 5; PIN Node = 'kbcol\[2\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { kbcol[2] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.400 ns) 7.000 ns seg7\[1\] 2 REG LC4_C12 1 " "Info: 2: + IC(2.500 ns) + CELL(1.400 ns) = 7.000 ns; Loc. = LC4_C12; Fanout = 1; REG Node = 'seg7\[1\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { kbcol[2] seg7[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 64.29 % " "Info: Total cell delay = 4.500 ns ( 64.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 35.71 % " "Info: Total interconnect delay = 2.500 ns ( 35.71 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "7.000 ns" { kbcol[2] seg7[1] } "NODE_NAME" } } }  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk seg7[1] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "7.000 ns" { kbcol[2] seg7[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk kbrow\[3\] kbrow\[3\]~reg0 9.600 ns register " "Info: Minimum tco from clock clk to destination pin kbrow\[3\] through register kbrow\[3\]~reg0 is 9.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_42 14 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns kbrow\[3\]~reg0 2 REG LC1_A9 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'kbrow\[3\]~reg0'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "2.000 ns" { clk kbrow[3]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk kbrow[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns kbrow\[3\]~reg0 1 REG LC1_A9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'kbrow\[3\]~reg0'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "" { kbrow[3]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(3.900 ns) 4.800 ns kbrow\[3\] 2 PIN Pin_37 0 " "Info: 2: + IC(0.900 ns) + CELL(3.900 ns) = 4.800 ns; Loc. = Pin_37; Fanout = 0; PIN Node = 'kbrow\[3\]'" {  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "4.800 ns" { kbrow[3]~reg0 kbrow[3] } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/key_scan.vhd" "" "" { Text "I:/VHDL/myprg/key_scan/key_scan.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 81.25 % " "Info: Total cell delay = 3.900 ns ( 81.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns 18.75 % " "Info: Total interconnect delay = 0.900 ns ( 18.75 % )" {  } {  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "4.800 ns" { kbrow[3]~reg0 kbrow[3] } "NODE_NAME" } } }  } 0}  } { { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "3.900 ns" { clk kbrow[3]~reg0 } "NODE_NAME" } } } { "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" "" "" { Report "I:/VHDL/myprg/key_scan/db/key_scan_cmp.qrpt" Compiler "key_scan" "UNKNOWN" "V1" "I:/VHDL/myprg/key_scan/db/key_scan.quartus_db" { Floorplan "" "" "4.800 ns" { kbrow[3]~reg0 kbrow[3] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 27 16:24:36 2008 " "Info: Processing ended: Thu Nov 27 16:24:36 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}