📄 key_scan.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key_scan is
port(clk :in std_logic;
start:in std_logic;
kbcol: in std_logic_vector(3 downto 0);--hang
kbrow: out std_logic_vector(3 downto 0);--lie
seg7_out:out std_logic_vector(3 downto 0));
end ;
architecture one of key_scan is
signal cnt:std_logic_vector(1 downto 0);
signal sta:std_logic_vector(1 downto 0);
signal seg7:std_logic_vector(3 downto 0);
signal dat:std_logic_vector(4 downto 0);
signal fn:std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then cnt<=cnt+1;end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
case cnt is
when "00"=>kbrow<="0001"; sta<="00";
when "01"=>kbrow<="0010"; sta<="01";
when "10"=>kbrow<="0100"; sta<="10";
when "11"=>kbrow<="1000"; sta<="11";
end case;
end if;
end process;
process(clk,start)
begin
if start='0' then seg7<="0000";
elsif clk'event and clk='1' then
case sta is
when "00"=>
case kbcol is
when "0001"=> seg7<="0011";dat<="00011";--3
when "0010"=> seg7<="0010";dat<="00010";--2
when "0100"=> seg7<="0001";dat<="00001";--1
when "1000"=> seg7<="0000";dat<="00000";--0
when others=> seg7<="0000";dat<="11111";
end case;
when "01"=>
case kbcol is
when "0001"=> seg7<="0111";dat<="00011";--7
when "0010"=> seg7<="0110";dat<="00010";--6
when "0100"=> seg7<="0101";dat<="00001";--5
when "1000"=> seg7<="0100";dat<="00000";--4
when others=> seg7<="0000";dat<="11111";
end case;
when "10"=>
case kbcol is
when "0001"=> seg7<="1011";dat<="00011";--b
when "0010"=> seg7<="1010";dat<="00010";--a
when "0100"=> seg7<="1001";dat<="00001";--9
when "1000"=> seg7<="1000";dat<="00000";--8
when others=> seg7<="0000";dat<="11111";
end case;
when "11"=>
case kbcol is
when "0001"=> seg7<="1111";dat<="00011";--f
when "0010"=> seg7<="1110";dat<="00010";--e
when "0100"=> seg7<="1101";dat<="00001";--d
when "1000"=> seg7<="1100";dat<="00000";--c
when others=> seg7<="0000";dat<="11111";
end case;
when others=> seg7<="0000";
end case;
end if;
end process;
fn<=not(dat(0)and dat(2)and dat(3)and dat(1));
process(fn)
begin
if fn'event and fn='1' then
seg7_out<=seg7;
end if;
end process;
end;
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