📄 key_scan.tan.rpt
字号:
; N/A ; None ; 9.600 ns ; kbrow[3]~reg0 ; kbrow[3] ; clk ;
+-------+--------------+------------+------------------+-------------+------------+
+-------------------------------------------------------------------------+
; th ;
+--------------------------------------------------------------------------
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+----------+---------+----------+
; N/A ; None ; -1.700 ns ; kbcol[2] ; seg7[1] ; clk ;
; N/A ; None ; -1.700 ns ; kbcol[2] ; seg7[0] ; clk ;
; N/A ; None ; -1.700 ns ; kbcol[1] ; seg7[1] ; clk ;
; N/A ; None ; -1.700 ns ; kbcol[1] ; seg7[0] ; clk ;
; N/A ; None ; -1.700 ns ; kbcol[0] ; seg7[1] ; clk ;
; N/A ; None ; -1.700 ns ; kbcol[0] ; seg7[0] ; clk ;
; N/A ; None ; -1.900 ns ; start ; dat[1] ; clk ;
; N/A ; None ; -1.900 ns ; start ; dat[3] ; clk ;
; N/A ; None ; -1.900 ns ; start ; dat[0] ; clk ;
; N/A ; None ; -4.400 ns ; kbcol[3] ; seg7[1] ; clk ;
; N/A ; None ; -4.400 ns ; kbcol[3] ; seg7[0] ; clk ;
; N/A ; None ; -5.000 ns ; kbcol[2] ; dat[1] ; clk ;
; N/A ; None ; -5.000 ns ; kbcol[2] ; dat[3] ; clk ;
; N/A ; None ; -5.000 ns ; kbcol[1] ; dat[1] ; clk ;
; N/A ; None ; -5.000 ns ; kbcol[1] ; dat[3] ; clk ;
; N/A ; None ; -5.000 ns ; kbcol[0] ; dat[1] ; clk ;
; N/A ; None ; -5.000 ns ; kbcol[0] ; dat[3] ; clk ;
; N/A ; None ; -5.500 ns ; kbcol[2] ; dat[0] ; clk ;
; N/A ; None ; -5.500 ns ; kbcol[1] ; dat[0] ; clk ;
; N/A ; None ; -5.500 ns ; kbcol[0] ; dat[0] ; clk ;
; N/A ; None ; -5.800 ns ; kbcol[2] ; seg7[3] ; clk ;
; N/A ; None ; -5.800 ns ; kbcol[1] ; seg7[3] ; clk ;
; N/A ; None ; -5.800 ns ; kbcol[0] ; seg7[3] ; clk ;
; N/A ; None ; -6.300 ns ; kbcol[2] ; seg7[2] ; clk ;
; N/A ; None ; -6.300 ns ; kbcol[1] ; seg7[2] ; clk ;
; N/A ; None ; -6.300 ns ; kbcol[0] ; seg7[2] ; clk ;
; N/A ; None ; -7.700 ns ; kbcol[3] ; dat[1] ; clk ;
; N/A ; None ; -7.700 ns ; kbcol[3] ; dat[3] ; clk ;
; N/A ; None ; -8.200 ns ; kbcol[3] ; dat[0] ; clk ;
; N/A ; None ; -8.500 ns ; kbcol[3] ; seg7[3] ; clk ;
; N/A ; None ; -9.000 ns ; kbcol[3] ; seg7[2] ; clk ;
+---------------+-------------+-----------+----------+---------+----------+
+-------------------------------------------------------------------------------------------------+
; Minimum tco ;
+--------------------------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+------------------+-------------+------------+
; N/A ; None ; 9.600 ns ; kbrow[3]~reg0 ; kbrow[3] ; clk ;
; N/A ; None ; 9.600 ns ; kbrow[2]~reg0 ; kbrow[2] ; clk ;
; N/A ; None ; 9.600 ns ; kbrow[1]~reg0 ; kbrow[1] ; clk ;
; N/A ; None ; 10.700 ns ; kbrow[0]~reg0 ; kbrow[0] ; clk ;
; N/A ; None ; 17.100 ns ; seg7_out[3]~reg0 ; seg7_out[3] ; clk ;
; N/A ; None ; 17.100 ns ; seg7_out[2]~reg0 ; seg7_out[2] ; clk ;
; N/A ; None ; 18.400 ns ; seg7_out[1]~reg0 ; seg7_out[1] ; clk ;
; N/A ; None ; 18.400 ns ; seg7_out[0]~reg0 ; seg7_out[0] ; clk ;
+---------------+------------------+----------------+------------------+-------------+------------+
+---------------------------+
; Timing Analyzer Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Thu Nov 27 16:24:35 2008
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off key_scan -c key_scan
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node clk is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock dat[0] as buffer
Info: Detected ripple clock dat[3] as buffer
Info: Detected ripple clock dat[1] as buffer
Info: Detected gated clock i94~20 as buffer
Info: Clock clk Internal fmax is restricted to 125.0 MHz between source register cnt[1] and destination register sta[1]
Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.500 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A6; Fanout = 6; REG Node = 'cnt[1]'
Info: 2: + IC(0.600 ns) + CELL(0.900 ns) = 1.500 ns; Loc. = LC6_A6; Fanout = 1; REG Node = 'sta[1]'
Info: Total cell delay = 0.900 ns ( 60.00 % )
Info: Total interconnect delay = 0.600 ns ( 40.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock clk to destination register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC6_A6; Fanout = 1; REG Node = 'sta[1]'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: - Longest clock path from clock clk to source register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_A6; Fanout = 6; REG Node = 'cnt[1]'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: + Micro clock to output delay of source is 0.900 ns
Info: + Micro setup delay of destination is 1.300 ns
Warning: Circuit may not operate. Detected 4 non-operational path(s) clocked by clock clk with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source pin or register seg7[1] and destination pin or register seg7_out[1]~reg0 for clock clk (Hold time is 7.0 ns)
Info: + Largest clock skew is 8.000 ns
Info: + Longest clock path from clock clk to destination register is 11.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'
Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC2_C3; Fanout = 1; REG Node = 'dat[1]'
Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 7.300 ns; Loc. = LC1_C3; Fanout = 4; COMB Node = 'i94~20'
Info: 4: + IC(4.600 ns) + CELL(0.000 ns) = 11.900 ns; Loc. = LC7_C12; Fanout = 1; REG Node = 'seg7_out[1]~reg0'
Info: Total cell delay = 4.700 ns ( 39.50 % )
Info: Total interconnect delay = 7.200 ns ( 60.50 % )
Info: - Shortest clock path from clock clk to source register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC4_C12; Fanout = 1; REG Node = 'seg7[1]'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: - Micro clock to output delay of source is 0.900 ns
Info: - Shortest register to register delay is 1.500 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C12; Fanout = 1; REG Node = 'seg7[1]'
Info: 2: + IC(0.600 ns) + CELL(0.900 ns) = 1.500 ns; Loc. = LC7_C12; Fanout = 1; REG Node = 'seg7_out[1]~reg0'
Info: Total cell delay = 0.900 ns ( 60.00 % )
Info: Total interconnect delay = 0.600 ns ( 40.00 % )
Info: + Micro hold delay of destination is 1.400 ns
Info: tsu for register seg7[2] (data pin = kbcol[3], clock pin = clk) is 11.700 ns
Info: + Longest pin to register delay is 14.300 ns
Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_25; Fanout = 5; PIN Node = 'kbcol[3]'
Info: 2: + IC(5.700 ns) + CELL(1.400 ns) = 10.200 ns; Loc. = LC3_C12; Fanout = 3; COMB Node = 'i~43'
Info: 3: + IC(2.700 ns) + CELL(1.400 ns) = 14.300 ns; Loc. = LC3_A6; Fanout = 1; REG Node = 'seg7[2]'
Info: Total cell delay = 5.900 ns ( 41.26 % )
Info: Total interconnect delay = 8.400 ns ( 58.74 % )
Info: + Micro setup delay of destination is 1.300 ns
Info: - Shortest clock path from clock clk to destination register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_A6; Fanout = 1; REG Node = 'seg7[2]'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: tco from clock clk to destination pin seg7_out[0] through register seg7_out[0]~reg0 is 18.900 ns
Info: + Longest clock path from clock clk to source register is 11.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'
Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC2_C3; Fanout = 1; REG Node = 'dat[1]'
Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 7.300 ns; Loc. = LC1_C3; Fanout = 4; COMB Node = 'i94~20'
Info: 4: + IC(4.600 ns) + CELL(0.000 ns) = 11.900 ns; Loc. = LC5_C12; Fanout = 1; REG Node = 'seg7_out[0]~reg0'
Info: Total cell delay = 4.700 ns ( 39.50 % )
Info: Total interconnect delay = 7.200 ns ( 60.50 % )
Info: + Micro clock to output delay of source is 0.900 ns
Info: + Longest register to pin delay is 6.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C12; Fanout = 1; REG Node = 'seg7_out[0]~reg0'
Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = Pin_59; Fanout = 0; PIN Node = 'seg7_out[0]'
Info: Total cell delay = 3.900 ns ( 63.93 % )
Info: Total interconnect delay = 2.200 ns ( 36.07 % )
Info: th for register seg7[1] (data pin = kbcol[2], clock pin = clk) is -1.700 ns
Info: + Longest clock path from clock clk to destination register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC4_C12; Fanout = 1; REG Node = 'seg7[1]'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: + Micro hold delay of destination is 1.400 ns
Info: - Shortest pin to register delay is 7.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_27; Fanout = 5; PIN Node = 'kbcol[2]'
Info: 2: + IC(2.500 ns) + CELL(1.400 ns) = 7.000 ns; Loc. = LC4_C12; Fanout = 1; REG Node = 'seg7[1]'
Info: Total cell delay = 4.500 ns ( 64.29 % )
Info: Total interconnect delay = 2.500 ns ( 35.71 % )
Info: Minimum tco from clock clk to destination pin kbrow[3] through register kbrow[3]~reg0 is 9.600 ns
Info: + Shortest clock path from clock clk to source register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_42; Fanout = 14; CLK Node = 'clk'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'kbrow[3]~reg0'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: + Micro clock to output delay of source is 0.900 ns
Info: + Shortest register to pin delay is 4.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'kbrow[3]~reg0'
Info: 2: + IC(0.900 ns) + CELL(3.900 ns) = 4.800 ns; Loc. = Pin_37; Fanout = 0; PIN Node = 'kbrow[3]'
Info: Total cell delay = 3.900 ns ( 81.25 % )
Info: Total interconnect delay = 0.900 ns ( 18.75 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
Info: Processing ended: Thu Nov 27 16:24:36 2008
Info: Elapsed time: 00:00:01
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