📄 key_scan.fit.rpt
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; clk ; 42 ; 14 ; Clock ; Pin ;
; start ; 3 ; 7 ; Async. clear / Clock enable ; Non-global ;
; i94~20 ; LC1_C3 ; 4 ; Clock ; Internal ;
+--------+--------+---------+-----------------------------+--------------+
+------------------------------------+
; Global & Other Fast Signals ;
+-------------------------------------
; Name ; Pin # ; Fan-Out ; Global ;
+--------+--------+---------+--------+
; clk ; 42 ; 14 ; yes ;
; i94~20 ; LC1_C3 ; 4 ; yes ;
+--------+--------+---------+--------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+----------------------------------
; Name ; Fan-Out ;
+------------------+--------------+
; cnt[0] ; 7 ;
; start ; 7 ;
; cnt[1] ; 6 ;
; kbcol[2] ; 5 ;
; kbcol[3] ; 5 ;
; kbcol[1] ; 5 ;
; kbcol[0] ; 5 ;
; i~43 ; 3 ;
; seg7_out[1]~reg0 ; 1 ;
; seg7[0] ; 1 ;
; seg7_out[2]~reg0 ; 1 ;
; i~48 ; 1 ;
; dat[0] ; 1 ;
; dat[3] ; 1 ;
; seg7[1] ; 1 ;
; dat[1] ; 1 ;
; seg7[2] ; 1 ;
; kbrow[1]~reg0 ; 1 ;
; seg7_out[3]~reg0 ; 1 ;
; kbrow[3]~reg0 ; 1 ;
; kbrow[0]~reg0 ; 1 ;
; sta[1] ; 1 ;
; seg7_out[0]~reg0 ; 1 ;
; i~46 ; 1 ;
; seg7[3] ; 1 ;
; kbrow[2]~reg0 ; 1 ;
+------------------+--------------+
+---------------------------------------------------------------------------------------------+
; Peripheral Signals ;
+----------------------------------------------------------------------------------------------
; Peripheral Signal ; Source ; Usage ; Dedicated Clock ; Peripheral Control Signal ; Polarity ;
+-------------------+--------+-------+-----------------+---------------------------+----------+
; i94~20 ; LC1_C3 ; Clock ; no ; yes ; +ve ;
+-------------------+--------+-------+-----------------+---------------------------+----------+
+-------------------------------------------+
; LAB ;
+--------------------------+----------------+
; Number of Logic Elements ; Number of LABs ;
+--------------------------+----------------+
; 0 ; 65 ;
; 1 ; 4 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 2 ;
+--------------------------+----------------+
+----------------------------------------------+
; Local Routing Interconnect ;
+-----------------------------+----------------+
; Local Routing Interconnects ; Number of LABs ;
+-----------------------------+----------------+
; 0 ; 69 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 2 ;
+-----------------------------+----------------+
+---------------------------------------------+
; LAB External Interconnect ;
+----------------------------+----------------+
; LAB External Interconnects ; Number of LABs ;
+----------------------------+----------------+
; 0 ; 65 ;
; 1 ; 2 ;
; 2 ; 3 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 1 ;
+----------------------------+----------------+
+----------------------------------------------------------------------------------------+
; Row Interconnect ;
+-----------------------------------------------------------------------------------------
; Row ; Interconnect Used ; Left Half Interconnect Used ; Right Half Interconnect Used ;
+-------+-------------------+-----------------------------+------------------------------+
; A ; 3 / 96 ( 3 % ) ; 4 / 48 ( 8 % ) ; 0 / 48 ( 0 % ) ;
; B ; 1 / 96 ( 1 % ) ; 0 / 48 ( 0 % ) ; 0 / 48 ( 0 % ) ;
; C ; 7 / 96 ( 7 % ) ; 4 / 48 ( 8 % ) ; 0 / 48 ( 0 % ) ;
; Total ; 11 / 288 ( 3 % ) ; 8 / 144 ( 5 % ) ; 0 / 144 ( 0 % ) ;
+-------+-------------------+-----------------------------+------------------------------+
+---------------------------+
; LAB Column Interconnect ;
+----------------------------
; Col. ; Interconnect Used ;
+-------+-------------------+
; 1 ; 0 / 24 ( 0 % ) ;
; 2 ; 0 / 24 ( 0 % ) ;
; 3 ; 1 / 24 ( 4 % ) ;
; 4 ; 0 / 24 ( 0 % ) ;
; 5 ; 0 / 24 ( 0 % ) ;
; 6 ; 2 / 24 ( 8 % ) ;
; 7 ; 1 / 24 ( 4 % ) ;
; 8 ; 0 / 24 ( 0 % ) ;
; 9 ; 1 / 24 ( 4 % ) ;
; 10 ; 0 / 24 ( 0 % ) ;
; 11 ; 0 / 24 ( 0 % ) ;
; 12 ; 2 / 24 ( 8 % ) ;
; 13 ; 1 / 24 ( 4 % ) ;
; 14 ; 0 / 24 ( 0 % ) ;
; 15 ; 0 / 24 ( 0 % ) ;
; 16 ; 0 / 24 ( 0 % ) ;
; 17 ; 0 / 24 ( 0 % ) ;
; 18 ; 0 / 24 ( 0 % ) ;
; 19 ; 0 / 24 ( 0 % ) ;
; 20 ; 1 / 24 ( 4 % ) ;
; 21 ; 1 / 24 ( 4 % ) ;
; 22 ; 0 / 24 ( 0 % ) ;
; 23 ; 0 / 24 ( 0 % ) ;
; 24 ; 0 / 24 ( 0 % ) ;
; Total ; 10 / 576 ( 1 % ) ;
+-------+-------------------+
+---------------------------+
; LAB Column Interconnect ;
+----------------------------
; Col. ; Interconnect Used ;
+-------+-------------------+
; 1 ; 0 / 24 ( 0 % ) ;
; Total ; 0 / 24 ( 0 % ) ;
+-------+-------------------+
+---------------------------------------------------+
; Fitter Resource Usage Summary ;
+----------------------------------------------------
; Resource ; Usage ;
+------------------------------+--------------------+
; Logic cells ; 22 / 576 ( 3 % ) ;
; Registers ; 18 / 576 ( 3 % ) ;
; Logic cells in carry chains ; 0 ;
; User inserted logic cells ; 0 ;
; I/O pins ; 14 / 59 ( 23 % ) ;
; -- Clock pins ; 0 ;
; -- Dedicated input pins ; 0 / 4 ( 0 % ) ;
; Global signals ; 2 ;
; EABs ; 0 / 3 ( 0 % ) ;
; Total memory bits ; 0 / 12,288 ( 0 % ) ;
; Total RAM block bits ; 0 / 12,288 ( 0 % ) ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 14 ;
; Total fan-out ; 79 ;
; Average fan-out ; 2.19 ;
+------------------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node ; Logic Cells ; Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
; |key_scan ; 22 (22) ; 18 ; 0 ; 14 ; 4 (4) ; 9 (9) ; 9 (9) ; 0 (0) ; |key_scan ;
+----------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
+--------------------------------------+
; Delay Chain Summary ;
+---------------------------------------
; Name ; Pin Type ; Pad to Core ;
+-------------+----------+-------------+
; clk ; Input ; OFF ;
; kbcol[0] ; Input ; OFF ;
; kbcol[1] ; Input ; OFF ;
; kbcol[2] ; Input ; OFF ;
; kbcol[3] ; Input ; OFF ;
; start ; Input ; OFF ;
; kbrow[3] ; Output ; OFF ;
; kbrow[2] ; Output ; OFF ;
; kbrow[1] ; Output ; OFF ;
; kbrow[0] ; Output ; OFF ;
; seg7_out[3] ; Output ; OFF ;
; seg7_out[2] ; Output ; OFF ;
; seg7_out[1] ; Output ; OFF ;
; seg7_out[0] ; Output ; OFF ;
+-------------+----------+-------------+
+---------------+
; Pin-Out File ;
+---------------+
The pin-out file can be found in I:/VHDL/myprg/key_scan/key_scan.pin.
+------------------+
; Fitter Messages ;
+------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Thu Nov 27 16:24:21 2008
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off key_scan -c key_scan
Info: Selected device EPF10K10LC84-3 for design key_scan
Info: Timing requirements not specified -- optimizing all clocks equally to maximize operation frequency
Info: Inserted 0 logic cells in first fitting attempt
Warning: Following nodes are assigned to locations or regions, but do not exist in design
Warning: Node scan[0] is assigned to location or region, but does not exist in design
Warning: Node scan[1] is assigned to location or region, but does not exist in design
Warning: Node scan[2] is assigned to location or region, but does not exist in design
Warning: Node scan[3] is assigned to location or region, but does not exist in design
Warning: Node scan[4] is assigned to location or region, but does not exist in design
Warning: Node scan[5] is assigned to location or region, but does not exist in design
Info: Started fitting attempt 1 on Thu Nov 27 2008 at 16:24:22
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement operations ending: elapsed time = 0 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Quartus II Fitter was successful. 0 errors, 7 warnings
Info: Processing ended: Thu Nov 27 16:24:26 2008
Info: Elapsed time: 00:00:04
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