digital_clk.map.qmsg

此程序是实现数字钟的

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clock_m digital_clk.vhd(147) " "Warning: VHDL Process Statement warning at digital_clk.vhd(147): signal clock_m is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 147 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clock_h digital_clk.vhd(148) " "Warning: VHDL Process Statement warning at digital_clk.vhd(148): signal clock_h is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 148 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk1hz digital_clk.vhd(149) " "Warning: VHDL Process Statement warning at digital_clk.vhd(149): signal clk1hz is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 149 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mclk_tmp digital_clk.vhd(150) " "Warning: VHDL Process Statement warning at digital_clk.vhd(150): signal mclk_tmp is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 150 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hclk_tmp digital_clk.vhd(151) " "Warning: VHDL Process Statement warning at digital_clk.vhd(151): signal hclk_tmp is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 151 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clock_m digital_clk.vhd(161) " "Warning: VHDL Process Statement warning at digital_clk.vhd(161): signal clock_m is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 161 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clock_h digital_clk.vhd(162) " "Warning: VHDL Process Statement warning at digital_clk.vhd(162): signal clock_h is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 162 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk1hz digital_clk.vhd(163) " "Warning: VHDL Process Statement warning at digital_clk.vhd(163): signal clk1hz is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 163 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mclk_tmp digital_clk.vhd(164) " "Warning: VHDL Process Statement warning at digital_clk.vhd(164): signal mclk_tmp is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 164 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hclk_tmp digital_clk.vhd(165) " "Warning: VHDL Process Statement warning at digital_clk.vhd(165): signal hclk_tmp is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 165 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "digital_clk.vhd(186) " "Info: VHDL Case Statement information at digital_clk.vhd(186): OTHERS choice is never selected" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 186 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "digital_clk.vhd(206) " "Info: VHDL Case Statement information at digital_clk.vhd(206): OTHERS choice is never selected" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 206 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "digital_clk.vhd(215) " "Info: VHDL Case Statement information at digital_clk.vhd(215): OTHERS choice is never selected" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 215 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "digital_clk.vhd(234) " "Info: VHDL Case Statement information at digital_clk.vhd(234): OTHERS choice is never selected" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 234 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "digital_clk.vhd(243) " "Info: VHDL Case Statement information at digital_clk.vhd(243): OTHERS choice is never selected" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 243 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "digital_clk.vhd(276) " "Info: VHDL Case Statement information at digital_clk.vhd(276): OTHERS choice is never selected" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 276 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "digital_clk.vhd(282) " "Info: VHDL Case Statement information at digital_clk.vhd(282): OTHERS choice is never selected" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 282 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "digital_clk.vhd(304) " "Info: VHDL Case Statement information at digital_clk.vhd(304): OTHERS choice is never selected" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 304 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(314) " "Warning: VHDL Process Statement warning at digital_clk.vhd(314): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 314 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(315) " "Warning: VHDL Process Statement warning at digital_clk.vhd(315): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 315 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(316) " "Warning: VHDL Process Statement warning at digital_clk.vhd(316): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 316 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(320) " "Warning: VHDL Process Statement warning at digital_clk.vhd(320): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 320 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(321) " "Warning: VHDL Process Statement warning at digital_clk.vhd(321): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 321 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(322) " "Warning: VHDL Process Statement warning at digital_clk.vhd(322): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 322 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(326) " "Warning: VHDL Process Statement warning at digital_clk.vhd(326): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 326 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(327) " "Warning: VHDL Process Statement warning at digital_clk.vhd(327): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 327 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(328) " "Warning: VHDL Process Statement warning at digital_clk.vhd(328): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 328 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(332) " "Warning: VHDL Process Statement warning at digital_clk.vhd(332): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 332 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(333) " "Warning: VHDL Process Statement warning at digital_clk.vhd(333): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 333 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "blink digital_clk.vhd(334) " "Warning: VHDL Process Statement warning at digital_clk.vhd(334): signal blink is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 334 0 0 } }  } 0}