digital_clk.map.qmsg

此程序是实现数字钟的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 25 14:27:12 2008 " "Info: Processing started: Thu Dec 25 14:27:12 2008" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off digital_clk -c digital_clk " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off digital_clk -c digital_clk" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "digital_clk.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file digital_clk.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 digital_clk-one " "Info: Found design unit 1: digital_clk-one" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "digital_clk-one" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 digital_clk " "Info: Found entity 1: digital_clk" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "digital_clk" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec digital_clk.vhd(111) " "Warning: VHDL Process Statement warning at digital_clk.vhd(111): signal sec is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 111 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min digital_clk.vhd(112) " "Warning: VHDL Process Statement warning at digital_clk.vhd(112): signal min is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 112 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour digital_clk.vhd(113) " "Warning: VHDL Process Statement warning at digital_clk.vhd(113): signal hour is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 113 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk1hz digital_clk.vhd(114) " "Warning: VHDL Process Statement warning at digital_clk.vhd(114): signal clk1hz is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 114 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mclk_tmp digital_clk.vhd(115) " "Warning: VHDL Process Statement warning at digital_clk.vhd(115): signal mclk_tmp is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 115 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hclk_tmp digital_clk.vhd(116) " "Warning: VHDL Process Statement warning at digital_clk.vhd(116): signal hclk_tmp is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 116 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min digital_clk.vhd(118) " "Warning: VHDL Process Statement warning at digital_clk.vhd(118): signal min is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clock_m digital_clk.vhd(118) " "Warning: VHDL Process Statement warning at digital_clk.vhd(118): signal clock_m is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour digital_clk.vhd(118) " "Warning: VHDL Process Statement warning at digital_clk.vhd(118): signal hour is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clock_h digital_clk.vhd(118) " "Warning: VHDL Process Statement warning at digital_clk.vhd(118): signal clock_h is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk2hz digital_clk.vhd(119) " "Warning: VHDL Process Statement warning at digital_clk.vhd(119): signal clk2hz is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 119 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec digital_clk.vhd(125) " "Warning: VHDL Process Statement warning at digital_clk.vhd(125): signal sec is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 125 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min digital_clk.vhd(126) " "Warning: VHDL Process Statement warning at digital_clk.vhd(126): signal min is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 126 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour digital_clk.vhd(127) " "Warning: VHDL Process Statement warning at digital_clk.vhd(127): signal hour is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 127 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk1hz digital_clk.vhd(128) " "Warning: VHDL Process Statement warning at digital_clk.vhd(128): signal clk1hz is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 128 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mclk_tmp digital_clk.vhd(129) " "Warning: VHDL Process Statement warning at digital_clk.vhd(129): signal mclk_tmp is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 129 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec digital_clk.vhd(132) " "Warning: VHDL Process Statement warning at digital_clk.vhd(132): signal sec is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 132 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min digital_clk.vhd(133) " "Warning: VHDL Process Statement warning at digital_clk.vhd(133): signal min is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 133 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour digital_clk.vhd(134) " "Warning: VHDL Process Statement warning at digital_clk.vhd(134): signal hour is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 134 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk1hz digital_clk.vhd(135) " "Warning: VHDL Process Statement warning at digital_clk.vhd(135): signal clk1hz is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 135 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hclk_tmp digital_clk.vhd(137) " "Warning: VHDL Process Statement warning at digital_clk.vhd(137): signal hclk_tmp is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec digital_clk.vhd(139) " "Warning: VHDL Process Statement warning at digital_clk.vhd(139): signal sec is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min digital_clk.vhd(140) " "Warning: VHDL Process Statement warning at digital_clk.vhd(140): signal min is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour digital_clk.vhd(141) " "Warning: VHDL Process Statement warning at digital_clk.vhd(141): signal hour is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mclk_tmp digital_clk.vhd(143) " "Warning: VHDL Process Statement warning at digital_clk.vhd(143): signal mclk_tmp is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hclk_tmp digital_clk.vhd(144) " "Warning: VHDL Process Statement warning at digital_clk.vhd(144): signal hclk_tmp is in statement, but is not in sensitivity list" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 144 0 0 } }  } 0}