digital_clk.tan.qmsg

此程序是实现数字钟的

{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "i461~1 " "Info: Node i461~1" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "i461~208 " "Info: Node i461~208" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } }  } 0}  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } } { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "i455~1 " "Info: Node i455~1" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "i455~225 " "Info: Node i455~225" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } }  } 0}  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } } { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } }  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 5 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "mode " "Info: Assuming node mode is an undefined clock" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 8 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "mode" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "inc " "Info: Assuming node inc is an undefined clock" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 9 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "inc" } } } }  } 0}  } {  } 0}
{ "Warning" "WTDB_RIPPLE_OR_GATED_CLOCKS_FOUND" "14 " "Warning: Found 14 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITDB_GATED_CLK" "i~16 " "Info: Detected gated clock i~16 as buffer" {  } { { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "i~16" } } } }  } 0} { "Info" "ITDB_GATED_CLK" "i~13 " "Info: Detected gated clock i~13 as buffer" {  } { { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "i~13" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "hclk_tmp " "Info: Detected ripple clock hclk_tmp as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 86 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "hclk_tmp" } } } }  } 0} { "Info" "ITDB_GATED_CLK" "i467~268 " "Info: Detected gated clock i467~268 as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "i467~268" } } } }  } 0} { "Info" "ITDB_GATED_CLK" "i461~209 " "Info: Detected gated clock i461~209 as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "i461~209" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "mclk_tmp " "Info: Detected ripple clock mclk_tmp as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 73 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "mclk_tmp" } } } }  } 0} { "Info" "ITDB_GATED_CLK" "i461~1 " "Info: Detected gated clock i461~1 as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "i461~1" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "state\[2\] " "Info: Detected ripple clock state\[2\] as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 65 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "state\[2\]" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "state\[0\] " "Info: Detected ripple clock state\[0\] as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 65 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "state\[0\]" } } } }  } 0} { "Info" "ITDB_GATED_CLK" "i461~211 " "Info: Detected gated clock i461~211 as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "i461~211" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "state\[1\] " "Info: Detected ripple clock state\[1\] as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 65 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "state\[1\]" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "clk1hz " "Info: Detected ripple clock clk1hz as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 46 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1hz" } } } }  } 0} { "Info" "ITDB_GATED_CLK" "i455~1 " "Info: Detected gated clock i455~1 as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 110 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "i455~1" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "clk1khz " "Info: Detected ripple clock clk1khz as buffer" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 36 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1khz" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:i75_rtl_5\|alt_counter_f10ke:wysi_counter\|q\[9\] register clk1khz 65.36 MHz 15.3 ns Internal " "Info: Clock clk has Internal fmax of 65.36 MHz between source register lpm_counter:i75_rtl_5\|alt_counter_f10ke:wysi_counter\|q\[9\] and destination register clk1khz (period= 15.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.100 ns + Longest register register " "Info: + Longest register to register delay is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:i75_rtl_5\|alt_counter_f10ke:wysi_counter\|q\[9\] 1 REG LC3_C16 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C16; Fanout = 3; REG Node = 'lpm_counter:i75_rtl_5\|alt_counter_f10ke:wysi_counter\|q\[9\]'" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { lpm_counter:i75_rtl_5|alt_counter_f10ke:wysi_counter|q[9] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 3.200 ns i~3868 2 COMB LC7_C13 1 " "Info: 2: + IC(1.800 ns) + CELL(1.400 ns) = 3.200 ns; Loc. = LC7_C13; Fanout = 1; COMB Node = 'i~3868'" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.200 ns" { lpm_counter:i75_rtl_5|alt_counter_f10ke:wysi_counter|q[9] i~3868 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 4.500 ns i~3881 3 COMB LC8_C13 1 " "Info: 3: + IC(0.000 ns) + CELL(1.300 ns) = 4.500 ns; Loc. = LC8_C13; Fanout = 1; COMB Node = 'i~3881'" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "1.300 ns" { i~3868 i~3881 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 8.200 ns i~3855 4 COMB LC8_C16 16 " "Info: 4: + IC(1.800 ns) + CELL(1.900 ns) = 8.200 ns; Loc. = LC8_C16; Fanout = 16; COMB Node = 'i~3855'" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.700 ns" { i~3881 i~3855 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.400 ns) 11.500 ns clk1khz~1 5 COMB LC2_C15 1 " "Info: 5: + IC(1.900 ns) + CELL(1.400 ns) = 11.500 ns; Loc. = LC2_C15; Fanout = 1; COMB Node = 'clk1khz~1'" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.300 ns" { i~3855 clk1khz~1 } "NODE_NAME" } } } { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.000 ns) 13.100 ns clk1khz 6 REG LC1_C15 25 " "Info: 6: + IC(0.600 ns) + CELL(1.000 ns) = 13.100 ns; Loc. = LC1_C15; Fanout = 25; REG Node = 'clk1khz'" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "1.600 ns" { clk1khz~1 clk1khz } "NODE_NAME" } } } { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 53.44 % " "Info: Total cell delay = 7.000 ns ( 53.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns 46.56 % " "Info: Total interconnect delay = 6.100 ns ( 46.56 % )" {  } {  } 0}  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.100 ns" { lpm_counter:i75_rtl_5|alt_counter_f10ke:wysi_counter|q[9] i~3868 i~3881 i~3855 clk1khz~1 clk1khz } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns clk1khz 2 REG LC1_C15 25 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_C15; Fanout = 25; REG Node = 'clk1khz'" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.000 ns" { clk clk1khz } "NODE_NAME" } } } { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { clk clk1khz } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_counter:i75_rtl_5\|alt_counter_f10ke:wysi_counter\|q\[9\] 2 REG LC3_C16 3 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_C16; Fanout = 3; REG Node = 'lpm_counter:i75_rtl_5\|alt_counter_f10ke:wysi_counter\|q\[9\]'" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.000 ns" { clk lpm_counter:i75_rtl_5|alt_counter_f10ke:wysi_counter|q[9] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { clk lpm_counter:i75_rtl_5|alt_counter_f10ke:wysi_counter|q[9] } "NODE_NAME" } } }  } 0}  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { clk clk1khz } "NODE_NAME" } } } { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { clk lpm_counter:i75_rtl_5|alt_counter_f10ke:wysi_counter|q[9] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" "" "" { Text "C:/Documents and Settings/user/桌面/digital_clk/digital_clk.vhd" 36 -1 0 } }  } 0}  } { { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.100 ns" { lpm_counter:i75_rtl_5|alt_counter_f10ke:wysi_counter|q[9] i~3868 i~3881 i~3855 clk1khz~1 clk1khz } "NODE_NAME" } } } { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { clk clk1khz } "NODE_NAME" } } } { "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { clk lpm_counter:i75_rtl_5|alt_counter_f10ke:wysi_counter|q[9] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_PATH_NOT_FOUND" "Clock mode lpm_counter:hour_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] " "Info: Can't find any paths of type Clock between source node mode and destination node lpm_counter:hour_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]" {  } {  } 0}