📄 444.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\05310204lppy\05310204lppy\444.rpt
444
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 4/ 48( 8%) 0/ 48( 0%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\05310204lppy\05310204lppy\444.rpt
444
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 cl
Device-Specific Information: e:\05310204lppy\05310204lppy\444.rpt
444
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 cr
Device-Specific Information: e:\05310204lppy\05310204lppy\444.rpt
444
** EQUATIONS **
cl : INPUT;
cr : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
e : INPUT;
f : INPUT;
fm : INPUT;
-- Node name is 'Q0'
-- Equation name is 'Q0', type is output
Q0 = _LC3_B8;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC8_B8;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = _LC1_B8;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = _LC6_B11;
-- Node name is '|74194:5|:41' = '|74194:5|QA'
-- Equation name is '_LC3_B8', type is buried
_LC3_B8 = DFFE( _EQ001, GLOBAL( cl), GLOBAL( cr), VCC, VCC);
_EQ001 = !_LC3_B8 & _LC7_B8
# e & _LC7_B8
# f & _LC7_B8
# !e & !f & _LC3_B8 & !_LC7_B8;
-- Node name is '|74194:5|:40' = '|74194:5|QB'
-- Equation name is '_LC8_B8', type is buried
_LC8_B8 = DFFE( _EQ002, GLOBAL( cl), GLOBAL( cr), VCC, VCC);
_EQ002 = f & _LC4_B8
# _LC4_B8 & !_LC8_B8
# e & _LC4_B8
# !e & !f & !_LC4_B8 & _LC8_B8;
-- Node name is '|74194:5|:39' = '|74194:5|QC'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = DFFE( _EQ003, GLOBAL( cl), GLOBAL( cr), VCC, VCC);
_EQ003 = !_LC1_B8 & _LC1_B11
# e & _LC1_B11
# f & _LC1_B11
# !e & !f & _LC1_B8 & !_LC1_B11;
-- Node name is '|74194:5|:38' = '|74194:5|QD'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = DFFE( _EQ004, GLOBAL( cl), GLOBAL( cr), VCC, VCC);
_EQ004 = _LC4_B11 & !_LC6_B11
# f & _LC4_B11
# e & _LC4_B11
# !e & !f & !_LC4_B11 & _LC6_B11;
-- Node name is '|74194:5|~46~1'
-- Equation name is '_LC3_B11', type is buried
-- synthesized logic cell
_LC3_B11 = LCELL( _EQ005);
_EQ005 = D3 & e
# !e & _LC1_B8;
-- Node name is '|74194:5|:46'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ006);
_EQ006 = f & _LC3_B11
# e & !f & fm;
-- Node name is '|74194:5|~47~1'
-- Equation name is '_LC2_B11', type is buried
-- synthesized logic cell
_LC2_B11 = LCELL( _EQ007);
_EQ007 = D2 & e
# !e & _LC8_B8;
-- Node name is '|74194:5|:47'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ008);
_EQ008 = f & _LC2_B11
# e & !f & _LC6_B11;
-- Node name is '|74194:5|~48~1'
-- Equation name is '_LC2_B8', type is buried
-- synthesized logic cell
_LC2_B8 = LCELL( _EQ009);
_EQ009 = !e & _LC3_B8
# D1 & e;
-- Node name is '|74194:5|:48'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = LCELL( _EQ010);
_EQ010 = f & _LC2_B8
# e & !f & _LC1_B8;
-- Node name is '|74194:5|~49~1'
-- Equation name is '_LC6_B8', type is buried
-- synthesized logic cell
_LC6_B8 = LCELL( _EQ011);
_EQ011 = !e & _LC5_B8
# D0 & e;
-- Node name is '|74194:5|:49'
-- Equation name is '_LC7_B8', type is buried
_LC7_B8 = LCELL( _EQ012);
_EQ012 = f & _LC6_B8
# e & !f & _LC8_B8;
-- Node name is '|74194:5|~62~1'
-- Equation name is '_LC5_B8', type is buried
-- synthesized logic cell
_LC5_B8 = LCELL( _EQ013);
_EQ013 = !_LC1_B8 & !_LC3_B8 & !_LC8_B8;
Project Information e:\05310204lppy\05310204lppy\444.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 20,045K
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