📄 6_10.rpt
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q16 = _LC8_A13;
-- Node name is 'q17'
-- Equation name is 'q17', type is output
q17 = _LC5_A19;
-- Node name is 'q18'
-- Equation name is 'q18', type is output
q18 = _LC1_A22;
-- Node name is 'q19'
-- Equation name is 'q19', type is output
q19 = _LC1_A19;
-- Node name is 'q20'
-- Equation name is 'q20', type is output
q20 = _LC6_B18;
-- Node name is 'q21'
-- Equation name is 'q21', type is output
q21 = _LC1_B20;
-- Node name is 'q22'
-- Equation name is 'q22', type is output
q22 = _LC5_B18;
-- Node name is 'q23'
-- Equation name is 'q23', type is output
q23 = _LC8_B20;
-- Node name is '|74390:30|:7' = '|74390:30|1QA'
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = DFFE(!_LC8_A13, !_LC2_C1, GLOBAL(!e), VCC, VCC);
-- Node name is '|74390:30|:6' = '|74390:30|1QB'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = DFFE(!_LC5_A19, _LC2_A19, GLOBAL(!e), VCC, VCC);
-- Node name is '|74390:30|:5' = '|74390:30|1QC'
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = DFFE(!_LC1_A22, !_LC5_A19, GLOBAL(!e), VCC, VCC);
-- Node name is '|74390:30|:3' = '|74390:30|1QD'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = DFFE( _EQ001, !_LC8_A13, GLOBAL(!e), VCC, VCC);
_EQ001 = !_LC1_A19 & _LC1_A22 & _LC5_A19;
-- Node name is '|74390:30|:34' = '|74390:30|2QA'
-- Equation name is '_LC6_B18', type is buried
_LC6_B18 = DFFE(!_LC6_B18, !_LC1_A19, !f, VCC, VCC);
-- Node name is '|74390:30|:33' = '|74390:30|2QB'
-- Equation name is '_LC1_B20', type is buried
_LC1_B20 = DFFE(!_LC1_B20, _LC2_B20, !f, VCC, VCC);
-- Node name is '|74390:30|:32' = '|74390:30|2QC'
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = DFFE(!_LC5_B18, !_LC1_B20, !f, VCC, VCC);
-- Node name is '|74390:30|:31' = '|74390:30|2QD'
-- Equation name is '_LC8_B20', type is buried
_LC8_B20 = DFFE( _EQ002, !_LC6_B18, !f, VCC, VCC);
_EQ002 = _LC1_B20 & _LC5_B18 & !_LC8_B20;
-- Node name is '|74390:30|:20'
-- Equation name is '_LC2_A19', type is buried
_LC2_A19 = LCELL( _EQ003);
_EQ003 = _LC1_A19
# !_LC8_A13;
-- Node name is '|74390:30|:29'
-- Equation name is '_LC2_B20', type is buried
_LC2_B20 = LCELL( _EQ004);
_EQ004 = _LC8_B20
# !_LC6_B18;
-- Node name is '|74390:31|:7' = '|74390:31|1QA'
-- Equation name is '_LC2_B5', type is buried
_LC2_B5 = DFFE(!_LC2_B5, !_LC3_B14, GLOBAL(!c), VCC, VCC);
-- Node name is '|74390:31|:6' = '|74390:31|1QB'
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = DFFE(!_LC3_C5, _LC1_C5, GLOBAL(!c), VCC, VCC);
-- Node name is '|74390:31|:5' = '|74390:31|1QC'
-- Equation name is '_LC6_C10', type is buried
_LC6_C10 = DFFE(!_LC6_C10, !_LC3_C5, GLOBAL(!c), VCC, VCC);
-- Node name is '|74390:31|:3' = '|74390:31|1QD'
-- Equation name is '_LC5_C5', type is buried
_LC5_C5 = DFFE( _EQ005, !_LC2_B5, GLOBAL(!c), VCC, VCC);
_EQ005 = _LC3_C5 & !_LC5_C5 & _LC6_C10;
-- Node name is '|74390:31|:34' = '|74390:31|2QA'
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = DFFE(!_LC6_C4, !_LC5_C5, GLOBAL(!d), VCC, VCC);
-- Node name is '|74390:31|:33' = '|74390:31|2QB'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = DFFE(!_LC1_C4, _LC2_C4, GLOBAL(!d), VCC, VCC);
-- Node name is '|74390:31|:32' = '|74390:31|2QC'
-- Equation name is '_LC4_C1', type is buried
_LC4_C1 = DFFE(!_LC4_C1, !_LC1_C4, GLOBAL(!d), VCC, VCC);
-- Node name is '|74390:31|:31' = '|74390:31|2QD'
-- Equation name is '_LC2_C1', type is buried
_LC2_C1 = DFFE( _EQ006, !_LC6_C4, GLOBAL(!d), VCC, VCC);
_EQ006 = _LC1_C4 & !_LC2_C1 & _LC4_C1;
-- Node name is '|74390:31|:20'
-- Equation name is '_LC1_C5', type is buried
_LC1_C5 = LCELL( _EQ007);
_EQ007 = _LC5_C5
# !_LC2_B5;
-- Node name is '|74390:31|:29'
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = LCELL( _EQ008);
_EQ008 = _LC2_C1
# !_LC6_C4;
-- Node name is '|74390:32|:7' = '|74390:32|1QA'
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = DFFE(!_LC2_C22, GLOBAL(!a), !r, VCC, VCC);
-- Node name is '|74390:32|:6' = '|74390:32|1QB'
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = DFFE(!_LC1_C22, _LC3_C22, !r, VCC, VCC);
-- Node name is '|74390:32|:5' = '|74390:32|1QC'
-- Equation name is '_LC4_C16', type is buried
_LC4_C16 = DFFE(!_LC4_C16, !_LC1_C22, !r, VCC, VCC);
-- Node name is '|74390:32|:3' = '|74390:32|1QD'
-- Equation name is '_LC8_C16', type is buried
_LC8_C16 = DFFE( _EQ009, !_LC2_C22, !r, VCC, VCC);
_EQ009 = _LC1_C22 & _LC4_C16 & !_LC8_C16;
-- Node name is '|74390:32|:34' = '|74390:32|2QA'
-- Equation name is '_LC2_C18', type is buried
_LC2_C18 = DFFE(!_LC2_C18, !_LC8_C16, GLOBAL(!b), VCC, VCC);
-- Node name is '|74390:32|:33' = '|74390:32|2QB'
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = DFFE(!_LC2_B14, _LC1_B14, GLOBAL(!b), VCC, VCC);
-- Node name is '|74390:32|:32' = '|74390:32|2QC'
-- Equation name is '_LC5_B17', type is buried
_LC5_B17 = DFFE(!_LC5_B17, !_LC2_B14, GLOBAL(!b), VCC, VCC);
-- Node name is '|74390:32|:31' = '|74390:32|2QD'
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = DFFE( _EQ010, !_LC2_C18, GLOBAL(!b), VCC, VCC);
_EQ010 = _LC2_B14 & !_LC3_B14 & _LC5_B17;
-- Node name is '|74390:32|:20'
-- Equation name is '_LC3_C22', type is buried
_LC3_C22 = LCELL( _EQ011);
_EQ011 = _LC8_C16
# !_LC2_C22;
-- Node name is '|74390:32|:29'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ012);
_EQ012 = _LC3_B14
# !_LC2_C18;
Project Information e:\05310204lppy\05310204lppy\6_10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,593K
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