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<html lang="en"><head><title>Using the GNU Compiler Collection (GCC)</title><meta http-equiv="Content-Type" content="text/html"><meta name="description" content="Using the GNU Compiler Collection (GCC)"><meta name="generator" content="makeinfo 4.6"><!--Copyright &copy; 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.   <p>Permission is granted to copy, distribute and/or modify this documentunder the terms of the GNU Free Documentation License, Version 1.2 orany later version published by the Free Software Foundation; with theInvariant Sections being "GNU General Public License" and "FundingFree Software", the Front-Cover texts being (a) (see below), and withthe Back-Cover Texts being (b) (see below).  A copy of the license isincluded in the section entitled "GNU Free Documentation License".   <p>(a) The FSF's Front-Cover Text is:   <p>A GNU Manual   <p>(b) The FSF's Back-Cover Text is:   <p>You have freedom to copy and modify this GNU Manual, like GNU     software.  Copies published by the Free Software Foundation raise     funds for GNU development.--><meta http-equiv="Content-Style-Type" content="text/css"><style type="text/css"><!--  pre.display { font-family:inherit }  pre.format  { font-family:inherit }  pre.smalldisplay { font-family:inherit; font-size:smaller }  pre.smallformat  { font-family:inherit; font-size:smaller }  pre.smallexample { font-size:smaller }  pre.smalllisp    { font-size:smaller }--></style></head><body><div class="node"><p>Node:&nbsp;<a name="DEC%20Alpha%20Options">DEC Alpha Options</a>,Next:&nbsp;<a rel="next" accesskey="n" href="DEC-Alpha-VMS-Options.html#DEC%20Alpha%2fVMS%20Options">DEC Alpha/VMS Options</a>,Previous:&nbsp;<a rel="previous" accesskey="p" href="HPPA-Options.html#HPPA%20Options">HPPA Options</a>,Up:&nbsp;<a rel="up" accesskey="u" href="Submodel-Options.html#Submodel%20Options">Submodel Options</a><hr><br></div><h3 class="subsection">DEC Alpha Options</h4><p>These <code>-m</code> options are defined for the DEC Alpha implementations:     <dl><dt><code>-mno-soft-float</code>     <dd><dt><code>-msoft-float</code>     <dd>Use (do not use) the hardware floating-point instructions forfloating-point operations.  When <code>-msoft-float</code> is specified,functions in <code>libgcc.a</code> will be used to perform floating-pointoperations.  Unless they are replaced by routines that emulate thefloating-point operations, or compiled in such a way as to call suchemulations routines, these routines will issue floating-pointoperations.   If you are compiling for an Alpha without floating-pointoperations, you must ensure that the library is built so as not to callthem.     <p>Note that Alpha implementations without floating-point operations arerequired to have floating-point registers.     <br><dt><code>-mfp-reg</code>     <dd><dt><code>-mno-fp-regs</code>     <dd>Generate code that uses (does not use) the floating-point register set. <code>-mno-fp-regs</code> implies <code>-msoft-float</code>.  If the floating-pointregister set is not used, floating point operands are passed in integerregisters as if they were integers and floating-point results are passedin <code>$0</code> instead of <code>$f0</code>.  This is a non-standard calling sequence,so any function with a floating-point argument or return value called by codecompiled with <code>-mno-fp-regs</code> must also be compiled with thatoption.     <p>A typical use of this option is building a kernel that does not use,and hence need not save and restore, any floating-point registers.     <br><dt><code>-mieee</code>     <dd>The Alpha architecture implements floating-point hardware optimized formaximum performance.  It is mostly compliant with the IEEE floatingpoint standard.  However, for full compliance, software assistance isrequired.  This option generates code fully IEEE compliant code<em>except</em> that the <var>inexact-flag</var> is not maintained (see below). If this option is turned on, the preprocessor macro <code>_IEEE_FP</code> isdefined during compilation.  The resulting code is less efficient but isable to correctly support denormalized numbers and exceptional IEEEvalues such as not-a-number and plus/minus infinity.  Other Alphacompilers call this option <code>-ieee_with_no_inexact</code>.     <br><dt><code>-mieee-with-inexact</code>     <dd>This is like <code>-mieee</code> except the generated code also maintainsthe IEEE <var>inexact-flag</var>.  Turning on this option causes thegenerated code to implement fully-compliant IEEE math.  In addition to<code>_IEEE_FP</code>, <code>_IEEE_FP_EXACT</code> is defined as a preprocessormacro.  On some Alpha implementations the resulting code may executesignificantly slower than the code generated by default.  Since there isvery little code that depends on the <var>inexact-flag</var>, you shouldnormally not specify this option.  Other Alpha compilers call thisoption <code>-ieee_with_inexact</code>.     <br><dt><code>-mfp-trap-mode=</code><var>trap-mode</var><code></code>     <dd>This option controls what floating-point related traps are enabled. Other Alpha compilers call this option <code>-fptm </code><var>trap-mode</var><code></code>. The trap mode can be set to one of four values:          <dl><dt><code>n</code>          <dd>This is the default (normal) setting.  The only traps that are enabledare the ones that cannot be disabled in software (e.g., division by zerotrap).          <br><dt><code>u</code>          <dd>In addition to the traps enabled by <code>n</code>, underflow traps are enabledas well.          <br><dt><code>su</code>          <dd>Like <code>su</code>, but the instructions are marked to be safe for softwarecompletion (see Alpha architecture manual for details).          <br><dt><code>sui</code>          <dd>Like <code>su</code>, but inexact traps are enabled as well. </dl>     <br><dt><code>-mfp-rounding-mode=</code><var>rounding-mode</var><code></code>     <dd>Selects the IEEE rounding mode.  Other Alpha compilers call this option<code>-fprm </code><var>rounding-mode</var><code></code>.  The <var>rounding-mode</var> can be oneof:          <dl><dt><code>n</code>          <dd>Normal IEEE rounding mode.  Floating point numbers are rounded towardsthe nearest machine number or towards the even machine number in caseof a tie.          <br><dt><code>m</code>          <dd>Round towards minus infinity.          <br><dt><code>c</code>          <dd>Chopped rounding mode.  Floating point numbers are rounded towards zero.          <br><dt><code>d</code>          <dd>Dynamic rounding mode.  A field in the floating point control register(<var>fpcr</var>, see Alpha architecture reference manual) controls therounding mode in effect.  The C library initializes this register forrounding towards plus infinity.  Thus, unless your program modifies the<var>fpcr</var>, <code>d</code> corresponds to round towards plus infinity. </dl>     <br><dt><code>-mtrap-precision=</code><var>trap-precision</var><code></code>     <dd>In the Alpha architecture, floating point traps are imprecise.  Thismeans without software assistance it is impossible to recover from afloating trap and program execution normally needs to be terminated. GCC can generate code that can assist operating system trap handlersin determining the exact location that caused a floating point trap. Depending on the requirements of an application, different levels ofprecisions can be selected:          <dl><dt><code>p</code>          <dd>Program precision.  This option is the default and means a trap handlercan only identify which program caused a floating point exception.          <br><dt><code>f</code>          <dd>Function precision.  The trap handler can determine the function thatcaused a floating point exception.          <br><dt><code>i</code>          <dd>Instruction precision.  The trap handler can determine the exactinstruction that caused a floating point exception. </dl>     <p>Other Alpha compilers provide the equivalent options called<code>-scope_safe</code> and <code>-resumption_safe</code>.     <br><dt><code>-mieee-conformant</code>     <dd>This option marks the generated code as IEEE conformant.  You must notuse this option unless you also specify <code>-mtrap-precision=i</code> and either<code>-mfp-trap-mode=su</code> or <code>-mfp-trap-mode=sui</code>.  Its only effectis to emit the line <code>.eflag 48</code> in the function prologue of thegenerated assembly file.  Under DEC Unix, this has the effect thatIEEE-conformant math library routines will be linked in.     <br><dt><code>-mbuild-constants</code>     <dd>Normally GCC examines a 32- or 64-bit integer constant tosee if it can construct it from smaller constants in two or threeinstructions.  If it cannot, it will output the constant as a literal andgenerate code to load it from the data segment at runtime.     <p>Use this option to require GCC to construct <em>all</em> integer constantsusing code, even if it takes more instructions (the maximum is six).     <p>You would typically use this option to build a shared library dynamicloader.  Itself a shared library, it must relocate itself in memorybefore it can find the variables and constants in its own data segment.     <br><dt><code>-malpha-as</code>     <dd><dt><code>-mgas</code>     <dd>Select whether to generate code to be assembled by the vendor-suppliedassembler (<code>-malpha-as</code>) or by the GNU assembler <code>-mgas</code>.     <br><dt><code>-mbwx</code>     <dd><dt><code>-mno-bwx</code>     <dd><dt><code>-mcix</code>     <dd><dt><code>-mno-cix</code>     <dd><dt><code>-mfix</code>     <dd><dt><code>-mno-fix</code>     <dd><dt><code>-mmax</code>     <dd><dt><code>-mno-max</code>     <dd>Indicate whether GCC should generate code to use the optional BWX,CIX, FIX and MAX instruction sets.  The default is to use the instructionsets supported by the CPU type specified via <code>-mcpu=</code> option or thatof the CPU on which GCC was built if none was specified.     <br><dt><code>-mfloat-vax</code>     <dd><dt><code>-mfloat-ieee</code>     <dd>Generate code that uses (does not use) VAX F and G floating pointarithmetic instead of IEEE single and double precision.     <br><dt><code>-mexplicit-relocs</code>     <dd><dt><code>-mno-explicit-relocs</code>     <dd>Older Alpha assemblers provided no way to generate symbol relocationsexcept via assembler macros.  Use of these macros does not allowoptimal instruction scheduling.  GNU binutils as of version 2.12supports a new syntax that allows the compiler to explicitly markwhich relocations should apply to which instructions.  This optionis mostly useful for debugging, as GCC detects the capabilities ofthe assembler when it is built and sets the default accordingly.     <br><dt><code>-msmall-data</code>     <dd><dt><code>-mlarge-data</code>     <dd>When <code>-mexplicit-relocs</code> is in effect, static data isaccessed via <dfn>gp-relative</dfn> relocations.  When <code>-msmall-data</code>is used, objects 8 bytes long or smaller are placed in a <dfn>small data area</dfn>(the <code>.sdata</code> and <code>.sbss</code> sections) and are accessed via16-bit relocations off of the <code>$gp</code> register.  This limits thesize of the small data area to 64KB, but allows the variables to bedirectly accessed via a single instruction.     <p>The default is <code>-mlarge-data</code>.  With this option the data areais limited to just below 2GB.  Programs that require more than 2GB ofdata must use <code>malloc</code> or <code>mmap</code> to allocate the data in theheap instead of in the program's data segment.     <p>When generating code for shared libraries, <code>-fpic</code> implies<code>-msmall-data</code> and <code>-fPIC</code> implies <code>-mlarge-data</code>.     <br><dt><code>-msmall-text</code>     <dd><dt><code>-mlarge-text</code>     <dd>When <code>-msmall-text</code> is used, the compiler assumes that thecode of the entire program (or shared library) fits in 4MB, and isthus reachable with a branch instruction.  When <code>-msmall-data</code>is used, the compiler can assume that all local symbols share thesame <code>$gp</code> value, and thus reduce the number of instructionsrequired for a function call from 4 to 1.     <p>The default is <code>-mlarge-text</code>.     <br><dt><code>-mcpu=</code><var>cpu_type</var><code></code>     <dd>Set the instruction set and instruction scheduling parameters formachine type <var>cpu_type</var>.  You can specify either the <code>EV</code>style name or the corresponding chip number.  GCC supports schedulingparameters for the EV4, EV5 and EV6 family of processors and willchoose the default values for the instruction set from the processoryou specify.  If you do not specify a processor type, GCC will defaultto the processor on which the compiler was built.     <p>Supported values for <var>cpu_type</var> are          <dl><dt><code>ev4</code>          <dd><dt><code>ev45</code>          <dd><dt><code>21064</code>          <dd>Schedules as an EV4 and has no instruction set extensions.          <br><dt><code>ev5</code>          <dd><dt><code>21164</code>          <dd>Schedules as an EV5 and has no instruction set extensions.          <br><dt><code>ev56</code>          <dd><dt><code>21164a</code>          <dd>Schedules as an EV5 and supports the BWX extension.          <br><dt><code>pca56</code>          <dd><dt><code>21164pc</code>          <dd><dt><code>21164PC</code>          <dd>Schedules as an EV5 and supports the BWX and MAX extensions.          <br><dt><code>ev6</code>          <dd><dt><code>21264</code>          <dd>Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.          <br><dt><code>ev67</code>          <dd><dt><code>21264a</code>          <dd>Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions. </dl>     <br><dt><code>-mtune=</code><var>cpu_type</var><code></code>     <dd>Set only the instruction scheduling parameters for machine type<var>cpu_type</var>.  The instruction set is not changed.     <br><dt><code>-mmemory-latency=</code><var>time</var><code></code>     <dd>Sets the latency the scheduler should assume for typical memoryreferences as seen by the application.  This number is highlydependent on the memory access patterns used by the applicationand the size of the external cache on the machine.     <p>Valid options for <var>time</var> are          <dl><dt><code></code><var>number</var><code></code>          <dd>A decimal number representing clock cycles.          <br><dt><code>L1</code>          <dd><dt><code>L2</code>          <dd><dt><code>L3</code>          <dd><dt><code>main</code>          <dd>The compiler contains estimates of the number of clock cycles for"typical" EV4 &amp; EV5 hardware for the Level 1, 2 &amp; 3 caches(also called Dcache, Scache, and Bcache), as well as to main memory. Note that L3 is only valid for EV5.     </dl>     </dl>   </body></html>
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