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<html lang="en"><head><title>Using the GNU Compiler Collection (GCC)</title><meta http-equiv="Content-Type" content="text/html"><meta name="description" content="Using the GNU Compiler Collection (GCC)"><meta name="generator" content="makeinfo 4.6"><!--Copyright © 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. <p>Permission is granted to copy, distribute and/or modify this documentunder the terms of the GNU Free Documentation License, Version 1.2 orany later version published by the Free Software Foundation; with theInvariant Sections being "GNU General Public License" and "FundingFree Software", the Front-Cover texts being (a) (see below), and withthe Back-Cover Texts being (b) (see below). A copy of the license isincluded in the section entitled "GNU Free Documentation License". <p>(a) The FSF's Front-Cover Text is: <p>A GNU Manual <p>(b) The FSF's Back-Cover Text is: <p>You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development.--><meta http-equiv="Content-Style-Type" content="text/css"><style type="text/css"><!-- pre.display { font-family:inherit } pre.format { font-family:inherit } pre.smalldisplay { font-family:inherit; font-size:smaller } pre.smallformat { font-family:inherit; font-size:smaller } pre.smallexample { font-size:smaller } pre.smalllisp { font-size:smaller }--></style></head><body><div class="node"><p>Node: <a name="RS%2f6000%20and%20PowerPC%20Options">RS/6000 and PowerPC Options</a>,Next: <a rel="next" accesskey="n" href="Darwin-Options.html#Darwin%20Options">Darwin Options</a>,Previous: <a rel="previous" accesskey="p" href="M32R-D-Options.html#M32R%2fD%20Options">M32R/D Options</a>,Up: <a rel="up" accesskey="u" href="Submodel-Options.html#Submodel%20Options">Submodel Options</a><hr><br></div><h3 class="subsection">IBM RS/6000 and PowerPC Options</h4><p>These <code>-m</code> options are defined for the IBM RS/6000 and PowerPC: <dl><dt><code>-mpower</code> <dd><dt><code>-mno-power</code> <dd><dt><code>-mpower2</code> <dd><dt><code>-mno-power2</code> <dd><dt><code>-mpowerpc</code> <dd><dt><code>-mno-powerpc</code> <dd><dt><code>-mpowerpc-gpopt</code> <dd><dt><code>-mno-powerpc-gpopt</code> <dd><dt><code>-mpowerpc-gfxopt</code> <dd><dt><code>-mno-powerpc-gfxopt</code> <dd><dt><code>-mpowerpc64</code> <dd><dt><code>-mno-powerpc64</code> <dd>GCC supports two related instruction set architectures for theRS/6000 and PowerPC. The <dfn>POWER</dfn> instruction set are thoseinstructions supported by the <code>rios</code> chip set used in the originalRS/6000 systems and the <dfn>PowerPC</dfn> instruction set is thearchitecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, andthe IBM 4xx microprocessors. <p>Neither architecture is a subset of the other. However there is alarge common subset of instructions supported by both. An MQregister is included in processors supporting the POWER architecture. <p>You use these options to specify which instructions are available on theprocessor you are using. The default value of these options isdetermined when configuring GCC. Specifying the<code>-mcpu=</code><var>cpu_type</var><code></code> overrides the specification of theseoptions. We recommend you use the <code>-mcpu=</code><var>cpu_type</var><code></code> optionrather than the options listed above. <p>The <code>-mpower</code> option allows GCC to generate instructions thatare found only in the POWER architecture and to use the MQ register. Specifying <code>-mpower2</code> implies <code>-power</code> and also allows GCCto generate instructions that are present in the POWER2 architecture butnot the original POWER architecture. <p>The <code>-mpowerpc</code> option allows GCC to generate instructions thatare found only in the 32-bit subset of the PowerPC architecture. Specifying <code>-mpowerpc-gpopt</code> implies <code>-mpowerpc</code> and also allowsGCC to use the optional PowerPC architecture instructions in theGeneral Purpose group, including floating-point square root. Specifying<code>-mpowerpc-gfxopt</code> implies <code>-mpowerpc</code> and also allows GCC touse the optional PowerPC architecture instructions in the Graphicsgroup, including floating-point select. <p>The <code>-mpowerpc64</code> option allows GCC to generate the additional64-bit instructions that are found in the full PowerPC64 architectureand to treat GPRs as 64-bit, doubleword quantities. GCC defaults to<code>-mno-powerpc64</code>. <p>If you specify both <code>-mno-power</code> and <code>-mno-powerpc</code>, GCCwill use only the instructions in the common subset of botharchitectures plus some special AIX common-mode calls, and will not usethe MQ register. Specifying both <code>-mpower</code> and <code>-mpowerpc</code>permits GCC to use any instruction from either architecture and toallow use of the MQ register; specify this for the Motorola MPC601. <br><dt><code>-mnew-mnemonics</code> <dd><dt><code>-mold-mnemonics</code> <dd>Select which mnemonics to use in the generated assembler code. With<code>-mnew-mnemonics</code>, GCC uses the assembler mnemonics defined forthe PowerPC architecture. With <code>-mold-mnemonics</code> it uses theassembler mnemonics defined for the POWER architecture. Instructionsdefined in only one architecture have only one mnemonic; GCC uses thatmnemonic irrespective of which of these options is specified. <p>GCC defaults to the mnemonics appropriate for the architecture inuse. Specifying <code>-mcpu=</code><var>cpu_type</var><code></code> sometimes overrides thevalue of these option. Unless you are building a cross-compiler, youshould normally not specify either <code>-mnew-mnemonics</code> or<code>-mold-mnemonics</code>, but should instead accept the default. <br><dt><code>-mcpu=</code><var>cpu_type</var><code></code> <dd>Set architecture type, register usage, choice of mnemonics, andinstruction scheduling parameters for machine type <var>cpu_type</var>. Supported values for <var>cpu_type</var> are <code>401</code>, <code>403</code>,<code>405</code>, <code>405fp</code>, <code>440</code>, <code>440fp</code>, <code>505</code>,<code>601</code>, <code>602</code>, <code>603</code>, <code>603e</code>, <code>604</code>,<code>604e</code>, <code>620</code>, <code>630</code>, <code>740</code>, <code>7400</code>,<code>7450</code>, <code>750</code>, <code>801</code>, <code>821</code>, <code>823</code>,<code>860</code>, <code>970</code>, <code>common</code>, <code>ec603e</code>, <code>G3</code>,<code>G4</code>, <code>G5</code>, <code>power</code>, <code>power2</code>, <code>power3</code>,<code>power4</code>, <code>power5</code>, <code>powerpc</code>, <code>powerpc64</code>,<code>rios</code>, <code>rios1</code>, <code>rios2</code>, <code>rsc</code>, and <code>rs64a</code>. <p><code>-mcpu=common</code> selects a completely generic processor. Codegenerated under this option will run on any POWER or PowerPC processor. GCC will use only the instructions in the common subset of botharchitectures, and will not use the MQ register. GCC assumes a genericprocessor model for scheduling purposes. <p><code>-mcpu=power</code>, <code>-mcpu=power2</code>, <code>-mcpu=powerpc</code>, and<code>-mcpu=powerpc64</code> specify generic POWER, POWER2, pure 32-bitPowerPC (i.e., not MPC601), and 64-bit PowerPC architecture machinetypes, with an appropriate, generic processor model assumed forscheduling purposes. <p>The other options specify a specific processor. Code generated underthose options will run best on that processor, and may not run at all onothers. <p>The <code>-mcpu</code> options automatically enable or disable thefollowing options: <code>-maltivec</code>, <code>-mhard-float</code>,<code>-mmfcrf</code>, <code>-mmultiple</code>, <code>-mnew-mnemonics</code>,<code>-mpower</code>, <code>-mpower2</code>, <code>-mpowerpc64</code>,<code>-mpowerpc-gpopt</code>, <code>-mpowerpc-gfxopt</code>,<code>-mstring</code>. The particular options set for any particular CPUwill vary between compiler versions, depending on what setting seemsto produce optimal code for that CPU; it doesn't necessarily reflectthe actual hardware's capabilities. If you wish to set an individualoption to a particular value, you may specify it after the<code>-mcpu</code> option, like <code>-mcpu=970 -mno-altivec</code>. <p>On AIX, the <code>-maltivec</code> and <code>-mpowerpc64</code> options arenot enabled or disabled by the <code>-mcpu</code> option at present, sinceAIX does not have full support for these options. You may stillenable or disable them individually if you're sure it'll work in yourenvironment. <br><dt><code>-mtune=</code><var>cpu_type</var><code></code> <dd>Set the instruction scheduling parameters for machine type<var>cpu_type</var>, but do not set the architecture type, register usage, orchoice of mnemonics, as <code>-mcpu=</code><var>cpu_type</var><code></code> would. The samevalues for <var>cpu_type</var> are used for <code>-mtune</code> as for<code>-mcpu</code>. If both are specified, the code generated will use thearchitecture, registers, and mnemonics set by <code>-mcpu</code>, but thescheduling parameters set by <code>-mtune</code>. <br><dt><code>-maltivec</code> <dd><dt><code>-mno-altivec</code> <dd>These switches enable or disable the use of built-in functions thatallow access to the AltiVec instruction set. You may also need to set<code>-mabi=altivec</code> to adjust the current ABI with AltiVec ABIenhancements. <br><dt><code>-mabi=spe</code> <dd>Extend the current ABI with SPE ABI extensions. This does not changethe default ABI, instead it adds the SPE ABI extensions to the currentABI. <br><dt><code>-mabi=no-spe</code> <dd>Disable Booke SPE ABI extensions for the current ABI. <br><dt><code>-misel=</code><var>yes/no</var><code></code> <dd><dt><code>-misel</code> <dd>This switch enables or disables the generation of ISEL instructions. <br><dt><code>-mspe=</code><var>yes/no</var><code></code> <dd><dt><code>-mspe</code> <dd>This switch enables or disables the generation of SPE simdinstructions. <br><dt><code>-mfloat-gprs=</code><var>yes/no</var><code></code> <dd><dt><code>-mfloat-gprs</code> <dd>This switch enables or disables the generation of floating pointoperations on the general purpose registers for architectures thatsupport it. This option is currently only available on the MPC8540. <br><dt><code>-mfull-toc</code> <dd><dt><code>-mno-fp-in-toc</code> <dd><dt><code>-mno-sum-in-toc</code> <dd><dt><code>-mminimal-toc</code> <dd>Modify generation of the TOC (Table Of Contents), which is created forevery executable file. The <code>-mfull-toc</code> option is selected bydefault. In that case, GCC will allocate at least one TOC entry foreach unique non-automatic variable reference in your program. GCCwill also place floating-point constants in the TOC. However, only16,384 entries are available in the TOC. <p>If you receive a linker error message that saying you have overflowedthe available TOC space, you can reduce the amount of TOC space usedwith the <code>-mno-fp-in-toc</code> and <code>-mno-sum-in-toc</code> options. <code>-mno-fp-in-toc</code> prevents GCC from putting floating-pointconstants in the TOC and <code>-mno-sum-in-toc</code> forces GCC togenerate code to calculate the sum of an address and a constant atrun-time instead of putting that sum into the TOC. You may specify oneor both of these options. Each causes GCC to produce very slightlyslower and larger code at the expense of conserving TOC space. <p>If you still run out of space in the TOC even when you specify both ofthese options, specify <code>-mminimal-toc</code> instead. This option causesGCC to make only one TOC entry for every file. When you specify thisoption, GCC will produce code that is slower and larger but whichuses extremely little TOC space. You may wish to use this optiononly on files that contain less frequently executed code. <br><dt><code>-maix64</code> <dd><dt><code>-maix32</code> <dd>Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit<code>long</code> type, and the infrastructure needed to support them. Specifying <code>-maix64</code> implies <code>-mpowerpc64</code> and<code>-mpowerpc</code>, while <code>-maix32</code> disables the 64-bit ABI andimplies <code>-mno-powerpc64</code>. GCC defaults to <code>-maix32</code>. <br><dt><code>-mxl-call</code> <dd><dt><code>-mno-xl-call</code> <dd>On AIX, pass floating-point arguments to prototyped functions beyond theregister save area (RSA) on the stack in addition to argument FPRs. TheAIX calling convention was extended but not initially documented tohandle an obscure K&R C case of calling a function that takes theaddress of its arguments with fewer arguments than declared. AIX XLcompilers access floating point arguments which do not fit in theRSA from the stack when a subroutine is compiled withoutoptimization. Because always storing floating-point arguments on thestack is inefficient and rarely needed, this option is not enabled bydefault and only is necessary when calling subroutines compiled by AIXXL compilers without optimization. <br><dt><code>-mpe</code> <dd>Support <dfn>IBM RS/6000 SP</dfn> <dfn>Parallel Environment</dfn> (PE). Link anapplication written to use message passing with special startup code toenable the application to run. The system must have PE installed in thestandard location (<code>/usr/lpp/ppe.poe/</code>), or the <code>specs</code> filemust be overridden with the <code>-specs=</code> option to specify theappropriate directory location. The Parallel Environment does notsupport threads, so the <code>-mpe</code> option and the <code>-pthread</code>option are incompatible. <br><dt><code>-malign-natural</code> <dd><dt><code>-malign-power</code> <dd>On AIX, Darwin, and 64-bit PowerPC GNU/Linux, the option<code>-malign-natural</code> overrides the ABI-defined alignment of largertypes, such as floating-point doubles, on their natural size-based boundary. The option <code>-malign-power</code> instructs GCC to follow the ABI-specifiedalignment rules. GCC defaults to the standard alignment defined in the ABI. <br><dt><code>-msoft-float</code> <dd><dt><code>-mhard-float</code> <dd>Generate code that does not use (uses) the floating-point register set. Software floating point emulation is provided if you use the<code>-msoft-float</code> option, and pass the option to GCC when linking. <br><dt><code>-mmultiple</code> <dd><dt><code>-mno-multiple</code> <dd>Generate code that uses (does not use) the load multiple wordinstructions and the store multiple word instructions. Theseinstructions are generated by default on POWER systems, and notgenerated on PowerPC systems. Do not use <code>-mmultiple</code> on littleendian PowerPC systems, since those instructions do not work when theprocessor is in little endian mode. The exceptions are PPC740 andPPC750 which permit the instructions usage in little endian mode. <br><dt><code>-mstring</code> <dd><dt><code>-mno-string</code> <dd>Generate code that uses (does not use) the load string instructionsand the store string word instructions to save multiple registers anddo small block moves. These instructions are generated by default onPOWER systems, and not generated on PowerPC systems. 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