mips-options.html

自己收集的linux入门到学懂高级编程书集 包括linux程序设计第三版

     <br><dt><code>-msoft-float</code>
     <dd>Do not use floating-point coprocessor instructions.  Implement
floating-point calculations using library calls instead.

     <br><dt><code>-msingle-float</code>
     <dd>Assume that the floating-point coprocessor only supports single-precision
operations.

     <dt><code>-mdouble-float</code>
     <dd>Assume that the floating-point coprocessor supports double-precision
operations.  This is the default.

     <br><dt><code>-mint64</code>
     <dd>Force <code>int</code> and <code>long</code> types to be 64 bits wide.  See
<code>-mlong32</code> for an explanation of the default and the way
that the pointer size is determined.

     <br><dt><code>-mlong64</code>
     <dd>Force <code>long</code> types to be 64 bits wide.  See <code>-mlong32</code> for
an explanation of the default and the way that the pointer size is
determined.

     <br><dt><code>-mlong32</code>
     <dd>Force <code>long</code>, <code>int</code>, and pointer types to be 32 bits wide.

     <p>The default size of <code>int</code>s, <code>long</code>s and pointers depends on
the ABI.  All the supported ABIs use 32-bit <code>int</code>s.  The n64 ABI
uses 64-bit <code>long</code>s, as does the 64-bit EABI; the others use
32-bit <code>long</code>s.  Pointers are the same size as <code>long</code>s,
or the same size as integer registers, whichever is smaller.

     <br><dt><code>-G </code><var>num</var><code></code>
     <dd>Put global and static items less than or equal to <var>num</var> bytes into
the small data or bss section instead of the normal data or bss section. 
This allows the data to be accessed using a single instruction.

     <p>All modules should be compiled with the same <code>-G </code><var>num</var><code></code>
value.

     <br><dt><code>-membedded-data</code>
     <dd><dt><code>-mno-embedded-data</code>
     <dd>Allocate variables to the read-only data section first if possible, then
next in the small data section if possible, otherwise in data.  This gives
slightly slower code than the default, but reduces the amount of RAM required
when executing, and thus may be preferred for some embedded systems.

     <br><dt><code>-muninit-const-in-rodata</code>
     <dd><dt><code>-mno-uninit-const-in-rodata</code>
     <dd>Put uninitialized <code>const</code> variables in the read-only data section. 
This option is only meaningful in conjunction with <code>-membedded-data</code>.

     <br><dt><code>-msplit-addresses</code>
     <dd><dt><code>-mno-split-addresses</code>
     <dd>Enable (disable) use of the <code>%hi()</code> and <code>%lo()</code> assembler
relocation operators.  This option has been superceded by
<code>-mexplicit-relocs</code> but is retained for backwards compatibility.

     <br><dt><code>-mexplicit-relocs</code>
     <dd><dt><code>-mno-explicit-relocs</code>
     <dd>Use (do not use) assembler relocation operators when dealing with symbolic
addresses.  The alternative, selected by <code>-mno-explicit-relocs</code>,
is to use assembler macros instead.

     <p><code>-mexplicit-relocs</code> is usually the default if GCC was configured
to use an assembler that supports relocation operators.  However, the
combination of <code>-mabicalls</code> and <code>-fno-unit-at-a-time</code>
implies <code>-mno-explicit-relocs</code> unless explicitly overridden. 
This is because, when generating abicalls, the choice of relocation
depends on whether a symbol is local or global.  In some rare cases,
GCC will not be able to decide this until the whole compilation unit
has been read.

     <br><dt><code>-mrnames</code>
     <dd><dt><code>-mno-rnames</code>
     <dd>Generate (do not generate) code that refers to registers using their
software names.  The default is <code>-mno-rnames</code>, which tells GCC
to use hardware names like <code>$4</code> instead of software names like
<code>a0</code>.  The only assembler known to support <code>-rnames</code> is
the Algorithmics assembler.

     <br><dt><code>-mcheck-zero-division</code>
     <dd><dt><code>-mno-check-zero-division</code>
     <dd>Trap (do not trap) on integer division by zero.  The default is
<code>-mcheck-zero-division</code>.

     <br><dt><code>-mmemcpy</code>
     <dd><dt><code>-mno-memcpy</code>
     <dd>Force (do not force) the use of <code>memcpy()</code> for non-trivial block
moves.  The default is <code>-mno-memcpy</code>, which allows GCC to inline
most constant-sized copies.

     <br><dt><code>-mlong-calls</code>
     <dd><dt><code>-mno-long-calls</code>
     <dd>Disable (do not disable) use of the <code>jal</code> instruction.  Calling
functions using <code>jal</code> is more efficient but requires the caller
and callee to be in the same 256 megabyte segment.

     <p>This option has no effect on abicalls code.  The default is
<code>-mno-long-calls</code>.

     <br><dt><code>-mmad</code>
     <dd><dt><code>-mno-mad</code>
     <dd>Enable (disable) use of the <code>mad</code>, <code>madu</code> and <code>mul</code>
instructions, as provided by the R4650 ISA.

     <br><dt><code>-mfused-madd</code>
     <dd><dt><code>-mno-fused-madd</code>
     <dd>Enable (disable) use of the floating point multiply-accumulate
instructions, when they are available.  The default is
<code>-mfused-madd</code>.

     <p>When multiply-accumulate instructions are used, the intermediate
product is calculated to infinite precision and is not subject to
the FCSR Flush to Zero bit.  This may be undesirable in some
circumstances.

     <br><dt><code>-nocpp</code>
     <dd>Tell the MIPS assembler to not run its preprocessor over user
assembler files (with a <code>.s</code> suffix) when assembling them.

     <br><dt><code>-mfix-r4000</code>
     <dd><dt><code>-mno-fix-r4000</code>
     <dd>Work around certain R4000 CPU errata:
          <ul>
<li>A double-word or a variable shift may give an incorrect result if executed
immediately after starting an integer division. 
<li>A double-word or a variable shift may give an incorrect result if executed
while an integer multiplication is in progress. 
<li>An integer division may give an incorrect result if started in a delay slot
of a taken branch or a jump. 
</ul>

     <br><dt><code>-mfix-r4400</code>
     <dd><dt><code>-mno-fix-r4400</code>
     <dd>Work around certain R4400 CPU errata:
          <ul>
<li>A double-word or a variable shift may give an incorrect result if executed
immediately after starting an integer division. 
</ul>

     <br><dt><code>-mfix-vr4120</code>
     <dd><dt><code>-mno-fix-vr4120</code>
     <dd>Work around certain VR4120 errata:
          <ul>
<li><code>dmultu</code> does not always produce the correct result. 
<li><code>div</code> and <code>ddiv</code> do not always produce the correct result if one
of the operands is negative. 
</ul>
     The workarounds for the division errata rely on special functions in
<code>libgcc.a</code>.  At present, these functions are only provided by
the <code>mips64vr*-elf</code> configurations.

     <p>Other VR4120 errata require a nop to be inserted between certain pairs of
instructions.  These errata are handled by the assembler, not by GCC itself.

     <br><dt><code>-mfix-sb1</code>
     <dd><dt><code>-mno-fix-sb1</code>
     <dd>Work around certain SB-1 CPU core errata. 
(This flag currently works around the SB-1 revision 2
"F1" and "F2" floating point errata.)

     <br><dt><code>-mflush-func=</code><var>func</var><code></code>
     <dd><dt><code>-mno-flush-func</code>
     <dd>Specifies the function to call to flush the I and D caches, or to not
call any such function.  If called, the function must take the same
arguments as the common <code>_flush_func()</code>, that is, the address of the
memory range for which the cache is being flushed, the size of the
memory range, and the number 3 (to flush both caches).  The default
depends on the target GCC was configured for, but commonly is either
<code>_flush_func</code> or <code>__cpu_flush</code>.

     <br><dt><code>-mbranch-likely</code>
     <dd><dt><code>-mno-branch-likely</code>
     <dd>Enable or disable use of Branch Likely instructions, regardless of the
default for the selected architecture.  By default, Branch Likely
instructions may be generated if they are supported by the selected
architecture.  An exception is for the MIPS32 and MIPS64 architectures
and processors which implement those architectures; for those, Branch
Likely instructions will not be generated by default because the MIPS32
and MIPS64 architectures specifically deprecate their use.

     <br><dt><code>-mfp-exceptions</code>
     <dd><dt><code>-mno-fp-exceptions</code>
     <dd>Specifies whether FP exceptions are enabled.  This affects how we schedule
FP instructions for some processors.  The default is that FP exceptions are
enabled.

     <p>For instance, on the SB-1, if FP exceptions are disabled, and we are emitting
64-bit code, then we can use both FP pipes.  Otherwise, we can only use one
FP pipe. 
</dl>

   </body></html>