bsc_init.h

Renesas(Hitachi SuperH)SH7708的UCOS2源码,uC/OS-II 版本2.52.

;*****************************************************************************
bcr1:		.equ	h'ffffff60	; Bus control register 1
bcr2:		.equ	h'ffffff62	; Bus control register 2
wcr1:		.equ	h'ffffff64	; Wait control register 1
wcr2:		.equ	h'ffffff66	; Wait control register 2
mcr:		.equ	h'ffffff68	; Memory control register
dcr:		.equ	h'ffffff6a	; DRAM control register
pcr:		.equ	h'ffffff6c	; PCMCIA control register
rtcsr:		.equ	h'ffffff6e	; Refresh timer control/status register
rtcnt:		.equ	h'ffffff70	; Refresh timer counter
rtcor:		.equ	h'ffffff72	; Refresh timer constant register
rfcr:		.equ	h'ffffff74	; Refresh count register
bcr3:		.equ	h'ffffff7e	; Bus control register 3
sdmr:		.equ	h'ffffe8c0	; CS3 area SDRAM mode register
mcscr0:		.equ	h'ffffff50	
mcscr1:		.equ	h'ffffff52	
mcscr2:		.equ	h'ffffff54	
mcscr3:		.equ	h'ffffff56	
mcscr4:		.equ	h'ffffff58	
mcscr5:		.equ	h'ffffff5a	
mcscr6:		.equ	h'ffffff5c	
mcscr7:		.equ	h'ffffff5e	




;*****************************************************************************
;	NAME = BSC REGISTER DATA TABLE 
;	DATE = '97/11/19
;	NAME = M.Hasumi
;	HIST = '97/11/19 M.Hasumi NEW
;	       '98/05/20 MS7709PR01 version
;	       '98/04/08 MS7709APR01 version
;	REMK = Memory map
;		CS0(long-word)
;		    h'00000000 - h'003fffff : EPROM area    (4MB)
;		    h'01000000 - h'013fffff : Flash ROM area(4MB)
;		    h'02000000 - h'03ffffff : External area (32MB)
;		CS1
;		    h'04000000 - h'07ffffff : SH7709A/SH7729 internal I/O register area
;		CS2(long-word)
;		    h'08000000 - h'0bffffff : External area(64MB)
;		CS3(long-word)
;		    h'0c000000 - h'0dffffff : SDRAM area(32MB)
;		CS4(word)
;		    h'10000000 - h'100fffff : ST-NIC(DP83902A) register area
;		    h'10100000 - h'103fffff : ST-NIC(DP83902A) external area
;		    h'10400000 - h'1041ffff : UltraI/O(FDC37C935) area
;		    h'10420000 - h'107fffff : UltraI/O(FDC37C935) external area
;		    h'10800000 - h'10800003 : Global SW area
;		    h'10800004 - h'10bfffff : Global SW external area
;		    h'10c00000 - h'10c00001 : Debug LED
;		    h'10c00002 - h'10ffffff : external Debug LED
;		    h'11000000 - h'113fffff : Remote controra area
;		    h'11400000 - h'1140001f : Board controle regster area
;		    h'11400020 - h'117fffff : external Board controle regster area
;		    h'11800000 - h'11ffffff
;		    h'12000000 - h'13ffffff : External area
;		CS5(long-word)
;		    h'14000000 - h'17ffffff ; External area(64MB)
;		CS6(word)
;		    h'18000000 - h'1bffffff ; MR-SHPC-01 area
;*****************************************************************************
bcr1_d:		.equ	h'0008	   
					; bit15    : Not pulled up		0
					; bit14    : Not pulled up		0
					; bit13    : HIZMEM    0   Control line High-Z
					; bit12    : HIZCNT    0   RAS,CAS High-Z
					; bit11    : ENDIAN    0   Read only
					; bit10- 9 : A0BST1-0  00  CS0 area ordinary memory
					; bit 8- 7 : A5BST1-0  00  CS5 area ordinary memory
					; bit 6- 5 : A6BST1-0  00  CS6 area ordinary memory
					; bit 4- 2 : DRAMTP2-0 010 CS2 area ordinary memory
					;                          CS3 area SDRAM
					; bit 1    : A5PCM     0   CS5 area normal memory
					; bit 0    : A6PCM     0   CS6 area PCMCIA

bcr2_d:		.equ	h'2ef0
					; bit15-14 : Reserved  00
					; bit13-12 : A6SZ1-0   10  CS6 area 16bit bus size
					; bit11-10 : A5SZ1-0   11  CS5 area 32bit bus size
					; bit 9- 8 : A4SZ1-0   10  CS4 area 16bit bus size
					; bit 7- 6 : A3SZ1-0   11  CS3 area 32bit bus size
					; bit 5- 4 : A2SZ1-0   11  CS2 area 32bit bus size
					; bit 3- 0 : Reserved  0000

bcr3_d:		.equ	h'0000
					; bit15    : EXTEND    0   BSCP normal mode
					; bit14    : Reserved  0
					; bit13-12 : TPC31-0   00  RAS precharge time   : 1 cycle
					; bit11-10 : RCD31-0   00  RAS-CAS delay        : 1 cycle
					; bit 9- 8 : TRAS31-0  00  CBR refresh RAS pulse: 2 cycle
					; bit 7- 6 : Reserved  00
					; bit 5- 4 : TPC21-0   00  RAS precharge time   : 1 cycle
					; bit 3- 2 : RCD21-0   00  RAS-CAS delay        : 1 cycle
					; bit 1- 0 : TRAS21-0  00  CBR refresh RAS pulse: 2 cycle

wcr1_d:		.equ	h'0c30
					; bit15	   : Waitsel   0
					; bit14    : Reserved  0
					; bit13-12 : A6IW1-0   00  CS6 area No idle cycles
					; bit11-10 : A5IW1-0   11  CS5 area 2 idle cycle inserted
					; bit 9- 8 : A4IW1-0   00  CS4 area No idle cycles
					; bit 7- 6 : A3IW1-0   00  CS3 area No idle cycles
					; bit 5- 4 : A2IW1-0   11  CS2 area 2 idle cycle inserted
					; bit 3- 2 : Reserved  00
					; bit 1- 0 : A0IW1-0   00  CS0 area No idle cycles

wcr2_d:		.equ	h'BEDD
					; bit15-13 : A6W2-0    011 CS6 area  3 wait cycle inserted
					; bit12-10 : A5W2-0    111 CS5 area 10 wait cycle inserted
					; bit 9- 7 : A4W2-0    011 CS4 area  3 wait cycle inserted
					; bit 6- 5 : A3W1-0    10  CS3 area CAS pulse 2 cycle
					; bit 4- 3 : A2W1-0    11  CS2 area  3 wait cycle inserted
					; bit 2- 0 : A0W2-0    011 CS0 area  3 wait cycle inserted

mcr_d:		.equ	h'002c
					; bit15-14 : TPC1-0    00  Precharge to active command period : 1-cycle
					; bit13-12 : RCD1-0    00  Active command to colum command(same bank) : 1-cycle
					; bit11-10 : TRW1-0L   00  Write recovery or data-in to precharge lead time : 1-cycle
					; bit 9- 8 : TRAS1-0   00  Ref/Active to Ref/Active command period : 2-cycle
					; bit 7    : RASD	   1   SDRAM bank active mode
					; bit 6    : BE        0   Not used
					; bit 5- 3 : AMX1-0    101 The low address begins with A10(8M*8bit products)
					; bit 2    : RFSH      1   Refresh enable
					; bit 1    : RMODE     0   Refresh mode         : CBR refresh
					; bit 0    : EDOMODE   0   Not used

dcr_d:		.equ	h'0000
					; bit15-14 : TPC1-0    00  RAS precharge time   : 1 cycle
					; bit13-12 : RCD1-0    00  RAS-CAS latency time : 1 cycle
					; bit11-10 : Reserved  00
					; bit 9- 8 : TRAS1-0   00  CBR refresh RAS pulse: 2 cycle
					; bit 7    : Reserved  0
					; bit 6    : BE        0   Burst disable
					; bit 5    : Reserved  0
					; bit 4- 3 : AMX1-0    00  Colmun address       : 8bit
					; bit 2    : RFSH      0   Refresh disable
					; bit 1    : RMODE     0   Refresh mode         : CBR refresh
					; bit 0    : Reserved  0

pcr_d:		.equ	h'0000
					; bit15    : CS6 area  wait cycle inserted  0
					; bit14    : CS5 area  wait cycle inserted  0
					; bit13-12 : Reserved  00
					; bit11    : A5TED2    0   CS5 area ADDRESS-OE/WE latency time : 0.5-cycle
					; bit10    : A6TED2    0   CS6 area ADDRESS-OE/WE latency time : 0.5-cycle
					; bit 9    : A5TEH2    0   CS5 area OE/WE-ADDRESS hold time    : 0.5-cycle
					; bit 8    : A6TEH2    0   CS6 area OE/WE-ADDRESS hold time    : 0.5-cycle
					; bit 7- 6 : A5TED1-0  00  CS5 area ADDRESS-OE/WE latency time : 0.5-cycle
					; bit 5- 4 : A6TED1-0  00  CS6 area ADDRESS-OE/WE latency time : 0.5-cycle
					; bit 3- 2 : A5TEH1-0  00  CS5 area OE/WE-ADDRESS hold time    : 0.5-cycle
					; bit 1- 0 : A6TEH1-0  00  CS6 area OE/WE-ADDRESS hold time    : 0.5-cycle

sdmr_d:		.equ	h'ffffe888
					; bit31-12 : SDRAM Address 
					; bit11- 0 : SDRAM regster

rtcsr_d:	.equ	h'a508

rtcnt_d:	.equ	h'a500		; RTCNT clear data

rtcor_d:	.equ	h'a580		; Refresh cycle

rfcr_d:		.equ	h'a400		; RFCR clear data

mcscr0_d:	.equ	h'0000	

mcscr1_d:	.equ	h'0000	

mcscr2_d:	.equ	h'0000	

mcscr3_d:	.equ	h'0000	

mcscr4_d:	.equ	h'0000	

mcscr5_d:	.equ	h'0000	

mcscr6_d:	.equ	h'0000	

mcscr7_d:	.equ	h'0000