intc.c

Renesas(Hitachi SuperH)SH7708的UCOS2源码,uC/OS-II 版本2.52.

/*---------------------------------------------------------------------------*/
/*  Interrupt Controller Module                                              */
/*  Author: Kuan, Yeou-Fuh                                                   */
/*---------------------------------------------------------------------------*/
#include "sh7707.h"
#include "machine.h"

void InitINTC ( void );
void EnableINT ( void );

void InitINTC ()
{
   /*Initial Interrupt mask */

   ICR0  = 0x8000;      /* NMI is detected by falling edge            */
   ICR1  = 0x0000;      /* MAI=0, All Interrupts are not masked.      */
                        /* Use IRQ3-IRQ0 four independent interrupt   */
                        /* NMI is masked when BL is 1.                */
                        /* IRQ5 - IRQ0 are detected by falling edge   */
   ICR2  = 0x0000;      /* Interrupt are detected at low level input  */
                        /* to the PINT pins.                          */
   INTER = 0x0000;      /* Disable PINT input interrupt requests      */

   /*-----------------------------------------------------------------*/
   /*  Set Priority levels form 0 to 15 for On-Chip Module Interrupt  */
   /*-----------------------------------------------------------------*/
   IPRA  = 0xF000;      /* TMU0,        TMU1,         TMU2,  RTC      */
   IPRB  = 0x0000;      /* WDT,         REF,          SCI0,  reserevd */
   IPRC  = 0x0000;      /* IRQ3,        IRQ2,         IRQ1,  IRQ0     */
   IPRD  = 0x0000;      /* PINT0-PINT7, PINT8-PINT15, IRQ5,  IRQ4     */
   IPRE  = 0x0000;      /* DMAC,        IrDA,         SCI2,  A/D      */
/*
   IRR0  = 0x00;
   IRR1  = 0x00;
   IRR2  = 0x00;
*/
}

void EnableINT ()
{
   int SR;

   SR    = get_cr();
   SR   &= 0xEFFFFF0F;  /* BL = 0, I3,I2,I1,I0 (Interrupt mask bits) = 0 */
   set_cr ( SR );
}