📄 os_cpu.h
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/*
*********************************************************************************************************
* uC/OS-II
* The Real-Time Kernel
*
* (c) Copyright 1992-1998, Jean J. Labrosse, Plantation, FL
* All Rights Reserved
*
* Hitachi SH3 Specific code
*
*
* File : OS_CPU.H
* By : Kuan, Yeou-Fuh
*********************************************************************************************************
*/
#include <machine.h>
#ifdef OS_CPU_GLOBALS
#define OS_CPU_EXT
#else
#define OS_CPU_EXT extern
#endif
/*
*********************************************************************************************************
* DATA TYPES
* (Compiler Specific)
*********************************************************************************************************
*/
typedef unsigned char BOOLEAN;
typedef unsigned char INT8U; /* Unsigned 8 bit quantity */
typedef signed char INT8S; /* Signed 8 bit quantity */
typedef unsigned short INT16U; /* Unsigned 16 bit quantity */
typedef signed short INT16S; /* Signed 16 bit quantity */
typedef unsigned long INT32U; /* Unsigned 32 bit quantity */
typedef signed long INT32S; /* Signed 32 bit quantity */
typedef float FP32; /* Single precision floating point */
typedef double FP64; /* Double precision floating point */
typedef unsigned long OS_STK; /* Each stack entry is 32-bit wide */
typedef unsigned long OS_CPU_SR; /* define for cpu_sr */
/* #define BYTE INT8S */ /* Define data types for backward compatibility ... */
/* #define UBYTE INT8U */ /* ... to uC/OS V1.xx. Not actually needed for ... */
/* #define WORD INT16S */ /* ... uC/OS-II. */
/* #define UWORD INT16U */
/* #define LONG INT32S */
/* #define ULONG INT32U */
OS_CPU_EXT void disable_ints (INT32U *a);
OS_CPU_EXT void enable_ints (INT32U *a);
OS_CPU_EXT INT32U vect_level;
/*
*********************************************************************************************************
* Hitachi SH3
*
* Method #2: Disable/Enable interrupts by preserving the state of interrupts. In other words, if
* interrupts were disabled before entering the critical section, they will be enabled when
* leaving the critical section.
*********************************************************************************************************
*/
#define OS_CRITICAL_METHOD 3
#if OS_CRITICAL_METHOD == 1
#define OS_ENTER_CRITICAL() (set_imask(15)) /* Disable interrupts */
#define OS_EXIT_CRITICAL() (set_imask(0)) /* Enable interrupts */
#endif
#if OS_CRITICAL_METHOD == 2
#define OS_ENTER_CRITICAL() disable_ints (&vect_level) /* Disable interrupts */
#define OS_EXIT_CRITICAL() enable_ints (&vect_level) /* Enable interrupts */
#endif
#if OS_CRITICAL_METHOD == 3
#define OS_ENTER_CRITICAL() cpu_sr = get_cr();
#define OS_EXIT_CRITICAL() set_cr(cpu_sr);
#endif
/*
*********************************************************************************************************
* Hitachi SH3 Miscellaneous
*********************************************************************************************************
*/
#define OS_STK_GROWTH 1 /* Stack grows from HIGH to LOW memory */
#define uCOS 33 /* Trap number used for context switch */
#define OS_TASK_SW() trapa (uCOS) /* intrinsic function to execute TRAPA instruction */
/*
*********************************************************************************************************
* GLOBAL VARIABLES
*********************************************************************************************************
*/
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