translator_mem.h

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   translator_mem.h
 *
 *  Author          :   Jose Prats - [e-mail]
 *
 *  Date            :
 *
 *  Function        :
 *
 */

#ifndef TRANSLATOR_MEM_H_INCLUDED
#define TRANSLATOR_MEM_H_INCLUDED

#include <systemc.h>
#include "mips.h"

SC_MODULE(TRANSLATOR_MEM)
{
  // translator has a regular memory interface
  sc_in< bool > clk;
  sc_in<bool> rst;
  
  //Definitions of Control Words and control signal to send to the NI to control the memory node
  sc_bv<16> control_CWeop_store;
  sc_bv<32> send_mem_CWeop;

  // input signals for the mudule.
  // current node's address

  sc_int<8> send_rel_xaddr; 
  sc_int<8> send_rel_yaddr;
  sc_bv<8> send_rel_xaddr_bit;
  sc_bv<8> send_rel_yaddr_bit;

  // The memory node's address, own node address and net dimension must to be fixed. IT'S A PARAMETER TO BE PROGRAMMED
  sc_in < sc_int<8> > xdimension;
  sc_in < sc_int<8> > ydimension;

  sc_int<8> xdimension_int;   
  sc_int<8> ydimension_int;


  //This signal is for the memory node. It is the relative address that the node used for sending the data
  sc_int<8> x_mem_rel_addr;
  sc_int<8> y_mem_rel_addr;

 
  //Signals from NI
  sc_in< sc_bv<32> > reg_data_out;
  sc_in< bool > data_rdy;
  sc_in< bool > rcv_packet_end;
  sc_in< bool > send_rdy;

  // Is the input signal from NI to know wheather we are writing or reading from the remote memory
  sc_in< bool > rd_wr;
  sc_signal< bool > rd_wr_buff;
  sc_signal< bool > rd_wr_tmp;

  //Data bus from remote memory
  sc_in< sc_bv<32> > rem_mem_dout;
  sc_signal< sc_bv<32> > rem_mem_dout_buff;

  // ports for the remote memory
  sc_out< sc_bv<DWORD> > rem_mem_addr;
  sc_out< sc_bv<DWORD> > rem_mem_din;
  sc_out< sc_bv<2> > rem_mem_r,rem_mem_w;

  sc_int<32> buffer_addr;
  sc_int<32> buffer_data;
  sc_int<32> buffer_rel_addr;

  // output signals for the mudule
  // For the device
  sc_out< bool > trans_dev_w, trans_dev_r;
  sc_out< sc_bv<DWORD> > trans_dev_din;
  sc_out< bool > trans_dev_wdata, trans_dev_waddr;
  sc_out< bool > trans_dev_send_eop;

  
  // internal signals

  sc_signal<bool> int_dev_wdata;
  sc_signal<bool> int_dev_waddr;
  sc_signal<bool> int_dev_send_eop;
  sc_signal<bool> int_ram_w;


  //for the receive FSM
  enum rcv_state_t {rcv_idle, write_addr, get_addr, write_data, mem_access, rd_wr_buff_down};

  sc_signal<rcv_state_t> rcv_current_state;
  sc_signal<rcv_state_t> rcv_next_state;
  
  //for the send FSM                                 
  enum send_state_t {send_idle, do_send_data, keep_data_on_bus, do_send_CW, wait_for_send, send_finish};		

  sc_signal<send_state_t> send_current_state;   
  sc_signal<send_state_t> send_next_state;     
  sc_signal<bool> do_send;    
  sc_signal<bool> is_send_rdy;    


  // the actual logic
  void translator_process();
  void rd_wr_buffer();
  void translatorFSM_receive();
  void rcv_change_state();
  
  void translatorFSM_send(); 
  void send_change_state();	


  SC_CTOR(TRANSLATOR_MEM){
        control_CWeop_store = "0000000000010010";

	SC_METHOD(translator_process);
        sensitive << clk << int_dev_wdata << int_dev_waddr << int_dev_send_eop;

        /*SC_METHOD(rd_wr_buffer);
	sensitive_pos << rd_wr_tmp; */

        SC_METHOD(translatorFSM_receive);
	sensitive << rcv_current_state << data_rdy << rd_wr_tmp << rem_mem_dout << rst;

        SC_METHOD(rcv_change_state);
	sensitive_pos << clk << rst;
	
	SC_METHOD(translatorFSM_send);    
	sensitive << send_current_state << do_send << is_send_rdy << rst;
	
        SC_METHOD(send_change_state);    
	sensitive_pos << clk << rst;
  }
};


#endif