hazard.cpp

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   hazard.h
 *
 *  Author          :   Sander Stuijk ([e-mail])
 *
 *  Date            :   July 23, 2002
 *
 *  Function        :   Hazard detection unit
 *
 *  History         :
 *      23-07-02    :   Initial version.
 *      13-12-02    :   Synthesizable version [e-mail]
 *
 */
 
#include "hazard.h"

void HAZARD::hazard_thread()
{
	sc_uint<W_HAZARDFLAG> 	hazard;
	sc_uint<W_BRANCHOP> 	branchop;
	sc_uint<W_REGDST> 		idexregdst_t;
	sc_uint<W_REGWRITE>		memwbregwrite_t, exmemregwrite_t, idexregwrite_t;
	sc_uint<AWORDREG> 		idexwriteregisterrt_t, idexwriteregisterrd_t, 
								exmemwriteregister_t,memwbwriteregister_t;
	sc_uint<DWORD> 			instr_t;
	sc_uint<AWORDREG> 		ifidreadregister1_t, ifidreadregister2_t;   
	
	//-> while (true) {
		#ifdef VERBOSE
			clog << "HAZARD DETECTION UNIT" << endl;
		#endif
		
		// Read input
		memwbregwrite_t = MEMWBRegWrite.read();
		exmemregwrite_t = EXMEMRegWrite.read();
		idexregwrite_t = IDEXRegWrite.read();
		idexregdst_t = IDEXRegDst.read();
		idexwriteregisterrt_t = IDEXWriteRegisterRt.read();
		idexwriteregisterrd_t = IDEXWriteRegisterRd.read();
		exmemwriteregister_t = EXMEMWriteRegister.read();
		memwbwriteregister_t = MEMWBWriteRegister.read();
		instr_t = Instr.read();
		branchop = BranchOp.read();
		
		// Read registers
		ifidreadregister1_t = instr_t.range(25,21);
		ifidreadregister2_t = instr_t.range(20,16);
		
        imem_en.write(1);
        dmem_en.write(1);
        pipe_en.write(1);
        
		// Compute output
		/*if( instr_t == 0 ){
		  // nop is not a hazard
		  hazard = 0;
		} else */
		if (branchop != 0) {
			// (Control) branch hazard
			// Don't fetch a new instruction, insert a 'nop'
			hazard = 1;
		}
		else if (idexregwrite_t == 1 &&
				((idexregdst_t == 0 && idexwriteregisterrt_t == ifidreadregister1_t) || 
					(idexregdst_t == 1 && idexwriteregisterrd_t == ifidreadregister1_t) || 
					(idexregdst_t == 0 && idexwriteregisterrt_t == ifidreadregister2_t) || 
					(idexregdst_t == 1 && idexwriteregisterrd_t == ifidreadregister2_t)))
		{
			// EX hazard
			hazard = 1;
		}
		else if (exmemregwrite_t == 1 && 
					((exmemwriteregister_t == ifidreadregister1_t) || 
						(exmemwriteregister_t == ifidreadregister2_t)))
		{
			// MEM hazard
			hazard = 1;
		}
		else if (memwbregwrite_t == 1 && 
					((memwbwriteregister_t == ifidreadregister1_t) || 
						(memwbwriteregister_t == ifidreadregister2_t)))
		{
			// WB hazard
			hazard = 1;
		}
		else
		{
			// No hazard
			hazard = 0;
		}
		
		// Write output
		if( enable.read()[0] == 0 )
		  {
			// block writing if not enabled
			PCWrite.write( 0 );
			IFIDWrite.write(0);
			Hazard.write( hazard );
            imem_en.write(0);
            dmem_en.write(0);
            pipe_en.write(0);
              
		  }
        else if( dmem_wait.read() || imem_wait.read() )
          {
			PCWrite.write( 0 );
			IFIDWrite.write(0);
			Hazard.write( hazard );
            if( dmem_wait.read() ) imem_en.write(0);
            if( imem_wait.read() ) dmem_en.write(0);
            pipe_en.write(0);            
          }
		else if (hazard)
		  {            
            // pre-fetch next instruction if it's branch hazard
			PCWrite.write( branchop ? 1 : 0 );
			imem_en.write( branchop ? 1 : 0 );
			IFIDWrite.write(0);
			Hazard.write(1);
		  }
		else
		{
          // In case this instruction is a branch, fetch the next instruction,
          // but don't change the program counter. The next instruction will
          // namely not be decoded duuring the next cycle. (we will insert a 'nop')
          if (instr_t.range(31,26) == 4 || instr_t.range(31,26) == 5){
            PCWrite.write( 0 );
            imem_en.write( 0 );
          }
          else {
            PCWrite.write( 1 );
            imem_en.write( 1 );
          }
			
          // regular output
          IFIDWrite.write( 1 );
          Hazard.write(0);
		}
		
		// Wait for new event
		//-> wait();	
//-> 	}
}

void HAZARD_CTRL::hazard_ctrl_thread()
{
	sc_bv<W_ALUOP> 		aluop;
	sc_bv<W_ALUSRC> 	alusrc;
	sc_bv<W_BRANCHOP> 	branch;
	sc_bv<W_HAZARDFLAG> hazard;
	sc_bv<W_MEMREAD> 	memread;
	sc_bv<W_MEMTOREG> 	memtoreg;
	sc_bv<W_MEMWRITE> 	memwrite;
	sc_bv<W_REGDST> 	regdst;
	sc_bv<W_REGVAL> 	regvalue;
	sc_bv<W_REGWRITE> 	regwrite;
	sc_bv<W_TARGET> 	target;

	//-> while (true){
		#ifdef VERBOSE
			clog << "HAZARD HANDLING UNIT" << endl;
		#endif

		// Read input
		hazard = Hazard.read();
		regdst = CtrlRegDst.read();
		regvalue = CtrlRegValue.read();
		target = CtrlTarget.read();
		branch = CtrlBranch.read();
		memread = CtrlMemRead.read();
		memtoreg = CtrlMemtoReg.read();
		aluop = CtrlALUop.read();
		memwrite = CtrlMemWrite.read();
		alusrc = CtrlALUSrc.read();
		regwrite = CtrlRegWrite.read();

		// Write output
		if (sc_uint<W_HAZARDFLAG>(hazard) == 0)
		{
			RegDst.write(regdst);
			RegValue.write(regvalue);
			Target.write(target);
			Branch.write(branch);
			MemRead.write(memread);
			MemtoReg.write(memtoreg);
			ALUop.write(aluop);
			MemWrite.write(memwrite);
			ALUSrc.write(alusrc);
			RegWrite.write(regwrite);
		}
		else
		{
			RegDst.write(0);
			RegValue.write(0);
			Target.write(0);
			Branch.write(0);
			MemRead.write(0);
			MemtoReg.write(0);
			ALUop.write(0);
			MemWrite.write(0);
			ALUSrc.write(0);
			RegWrite.write(0);
		}
		
		// Wait for new event
		//-> wait();	
//-> 	}
}