benif_network2x3.h

改进的基于6个mips核的NOC网络

#include <systemc.h>
#include "netmips.h"
#include "network2x3.h"

SC_MODULE(BENIF_NET_WRAPPER)
{
  sc_in< bool > IFCLK;
  sc_in< bool > WRITE_STROBE;
  sc_in< bool > READ_STROBE;
  sc_in< bool > DMA_ENABLE;
  sc_in< bool > DMA_DIRECTION;
  sc_in< bool > DMA_RDY;
  sc_in< bool > DMA_DATA_AVAILABLE;
  sc_in< bool > RST;
  sc_in< bool > SYNC_RESET;
  sc_in< bool > DMA_RESET;

  sc_in< sc_uint<31> > ADDRESS;
  sc_inout_rv< 32 > DATA;

  sc_inout_rv< 32 > DMA_DATA;
  sc_in< sc_uint<32> > COUNT;
  sc_in< sc_uint<4> > DMA_SEL;

  sc_out< bool > DMA_WEN;
  sc_out< bool > DMA_REN;
  sc_out< bool > INT;

  sc_out< sc_bv<4> > LEDS;

  sc_out<sc_uint<32> > memADDR;
  sc_out<sc_int<32> > memDI;
  sc_out<bool> memEN;
  sc_out<bool> memCLK;
  sc_out<bool> memRST;
  sc_in<sc_int<32> > ramDO0,romDO0,ramDO1,romDO1,ramDO2,romDO2,ramDO3,romDO3,ramDO4,romDO4,ramDO5,romDO5;
  sc_out<bool> ramWE0,romWE0,ramWE1,romWE1,ramWE2,romWE2,ramWE3,romWE3,ramWE4,romWE4,ramWE5,romWE5;
  sc_in<sc_bv<32> > pc0,pc1,pc2,pc3,pc4,pc5;
  sc_out<bool> enable0,enable1,enable2,enable3,enable4,enable5;
  sc_out<bool> reset;

#ifdef USEXRAM
  sc_out<sc_uint<32> > xADDR;
  sc_out<bool> xCLK;
  sc_in<sc_int<32> > xDO0,xDO1,xDO2,xDO3,xDO4,xDO5;
  sc_out<bool> xWE0,xWE1,xWE2,xWE3,xWE4,xWE5;
#endif

  sc_signal< sc_uint<32> > addr;
  sc_signal< sc_uint<32> > memsel;
  sc_signal< sc_uint<25> > cnt;
  
  sc_signal< sc_uint<32> > control;
  
  void logic();
  void count();
  void register_write();
  void register_read();
  void memory_input();
  
  SC_CTOR(BENIF_NET_WRAPPER)
  {
    SC_METHOD(logic);
    sensitive << IFCLK << WRITE_STROBE << READ_STROBE << DMA_ENABLE 
              << DMA_DIRECTION << DMA_RDY << DMA_DATA_AVAILABLE
              << RST << SYNC_RESET << DMA_RESET
              << ADDRESS << DATA
              << DMA_DATA << COUNT << DMA_SEL
              << control << addr << memsel << cnt;

    SC_METHOD(memory_input);
    sensitive << IFCLK << DATA << addr << memsel << ADDRESS << WRITE_STROBE << control;

    SC_METHOD(count);
    sensitive_pos << IFCLK << RST;
    
    SC_METHOD(register_write);
    sensitive_pos << IFCLK << RST;
    
    SC_METHOD(register_read);
    sensitive << READ_STROBE << ADDRESS << addr << memsel;
  sensitive << pc0 << pc1 << pc2 << pc3 << pc4 << pc5;
  sensitive << ramDO0 << romDO0 << ramDO1 << romDO1 << ramDO2 << romDO2 << ramDO3 << romDO3 << ramDO4 << romDO4 << ramDO5 << romDO5;
#ifdef USEXRAM
  sensitive << xDO0 << xDO1 << xDO2 << xDO3 << xDO4 << xDO5;
#endif
  }
};

SC_MODULE(BENIF_NET)
{
  NETWORK2x3 *network2x3;
  NETmMIPS *dp_x0y0;
  NETmMIPS *dp_x1y0;
  NETmMIPS *dp_x0y1;
  NETmMIPS *dp_x1y1;
  NETmMIPS *dp_x0y2;
  NETmMIPS *dp_x1y2;
  BENIF_NET_WRAPPER *wrapper;

  
  sc_in<bool>   MIPSCLK;
  
  sc_in< bool > IFCLK;
  sc_in< bool > WRITE_STROBE;
  sc_in< bool > READ_STROBE;
  sc_in< bool > DMA_ENABLE;
  sc_in< bool > DMA_DIRECTION;
  sc_in< bool > DMA_RDY;
  sc_in< bool > DMA_DATA_AVAILABLE;
  sc_in< bool > RST;
  sc_in< bool > SYNC_RESET;
  sc_in< bool > DMA_RESET;

  sc_in< sc_uint<31> > ADDRESS;
  sc_inout_rv< 32 > DATA;
  sc_inout_rv< 32 > DMA_DATA;
  sc_in< sc_uint<32> > COUNT;
  sc_in< sc_uint<4> > DMA_SEL;

  sc_out< bool > DMA_WEN;
  sc_out< bool > DMA_REN;
  sc_out< bool > INT;
  sc_out< sc_bv<4> > LEDS;

  sc_signal<sc_uint<32> > memADDR;
  sc_signal<sc_int<32> > memDI;
  sc_signal<bool> memEN;
  sc_signal<bool> memCLK;
  sc_signal<bool> memRST;

  sc_signal<sc_int<32> > ramDO0,romDO0,ramDO1,romDO1,ramDO2,romDO2,ramDO3,romDO3,ramDO4,romDO4,ramDO5,romDO5;
  sc_signal<bool> ramWE0,romWE0,ramWE1,romWE1,ramWE2,romWE2,ramWE3,romWE3,ramWE4,romWE4,ramWE5,romWE5;
  sc_signal<sc_bv<32> > pc0,pc1,pc2,pc3,pc4,pc5;
  sc_signal<bool> enable0,enable1,enable2,enable3,enable4,enable5;
  sc_signal<bool> reset;

#ifdef USEXRAM
  sc_signal<sc_uint<32> > xADDR;
  sc_signal<bool> xCLK;
  sc_signal<sc_int<32> > xDO0,xDO1,xDO2,xDO3,xDO4,xDO5;
  sc_signal<bool> xWE0,xWE1,xWE2,xWE3,xWE4,xWE5;
#endif
  sc_signal< sc_bv<FLIT_LEN> > x0y0din;
  sc_signal< sc_bv<FLIT_LEN> > x0y0dout;
  sc_signal<bool> x0y0req_net;
  sc_signal<bool> x0y0ack_net;
  sc_signal<bool> x0y0ack_dp;
  sc_signal<bool> x0y0req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x1y0din;
  sc_signal< sc_bv<FLIT_LEN> > x1y0dout;
  sc_signal<bool> x1y0req_net;
  sc_signal<bool> x1y0ack_net;
  sc_signal<bool> x1y0ack_dp;
  sc_signal<bool> x1y0req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x0y1din;
  sc_signal< sc_bv<FLIT_LEN> > x0y1dout;
  sc_signal<bool> x0y1req_net;
  sc_signal<bool> x0y1ack_net;
  sc_signal<bool> x0y1ack_dp;
  sc_signal<bool> x0y1req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x1y1din;
  sc_signal< sc_bv<FLIT_LEN> > x1y1dout;
  sc_signal<bool> x1y1req_net;
  sc_signal<bool> x1y1ack_net;
  sc_signal<bool> x1y1ack_dp;
  sc_signal<bool> x1y1req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x0y2din;
  sc_signal< sc_bv<FLIT_LEN> > x0y2dout;
  sc_signal<bool> x0y2req_net;
  sc_signal<bool> x0y2ack_net;
  sc_signal<bool> x0y2ack_dp;
  sc_signal<bool> x0y2req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x1y2din;
  sc_signal< sc_bv<FLIT_LEN> > x1y2dout;
  sc_signal<bool> x1y2req_net;
  sc_signal<bool> x1y2ack_net;
  sc_signal<bool> x1y2ack_dp;
  sc_signal<bool> x1y2req_dp;

  SC_CTOR(BENIF_NET)
  {
    network2x3 = new NETWORK2x3("network2x3");
    dp_x0y0 = new NETmMIPS("dp_x0y0");
    dp_x1y0 = new NETmMIPS("dp_x1y0");
    dp_x0y1 = new NETmMIPS("dp_x0y1");
    dp_x1y1 = new NETmMIPS("dp_x1y1");
    dp_x0y2 = new NETmMIPS("dp_x0y2");
    dp_x1y2 = new NETmMIPS("dp_x1y2");
    wrapper = new BENIF_NET_WRAPPER("wrapper");

    wrapper->reset(reset);
    wrapper->enable0(enable0);
    wrapper->enable1(enable1);
    wrapper->enable2(enable2);
    wrapper->enable3(enable3);
    wrapper->enable4(enable4);
    wrapper->enable5(enable5);
    wrapper->IFCLK(IFCLK);
    wrapper->WRITE_STROBE(WRITE_STROBE);
    wrapper->READ_STROBE(READ_STROBE);
    wrapper->DMA_ENABLE(DMA_ENABLE);
    wrapper->DMA_DIRECTION(DMA_DIRECTION);
    wrapper->DMA_RDY(DMA_RDY);
    wrapper->DMA_DATA_AVAILABLE(DMA_DATA_AVAILABLE);
    wrapper->RST(RST);
    wrapper->SYNC_RESET(SYNC_RESET);
    wrapper->DMA_RESET(DMA_RESET);
    wrapper->ADDRESS(ADDRESS);
    wrapper->DATA(DATA);
    wrapper->DMA_DATA(DMA_DATA);
    wrapper->COUNT(COUNT);
    wrapper->DMA_SEL(DMA_SEL);
    wrapper->DMA_WEN(DMA_WEN);
    wrapper->DMA_REN(DMA_REN);
    wrapper->INT(INT);
    wrapper->LEDS(LEDS);

    wrapper->memADDR(memADDR);
    wrapper->memDI(memDI);
    wrapper->memEN(memEN);
    wrapper->memCLK(memCLK);
    wrapper->memRST(memRST);
    wrapper->ramDO0(ramDO0);
    wrapper->ramWE0(ramWE0);
    wrapper->romDO0(romDO0);
    wrapper->romWE0(romWE0);
    wrapper->ramDO1(ramDO1);
    wrapper->ramWE1(ramWE1);
    wrapper->romDO1(romDO1);
    wrapper->romWE1(romWE1);
    wrapper->ramDO2(ramDO2);
    wrapper->ramWE2(ramWE2);
    wrapper->romDO2(romDO2);
    wrapper->romWE2(romWE2);
    wrapper->ramDO3(ramDO3);
    wrapper->ramWE3(ramWE3);
    wrapper->romDO3(romDO3);
    wrapper->romWE3(romWE3);
    wrapper->ramDO4(ramDO4);
    wrapper->ramWE4(ramWE4);
    wrapper->romDO4(romDO4);
    wrapper->romWE4(romWE4);
    wrapper->ramDO5(ramDO5);
    wrapper->ramWE5(ramWE5);
    wrapper->romDO5(romDO5);
    wrapper->romWE5(romWE5);

    dp_x0y0->ramADDR(memADDR); dp_x0y0->romADDR(memADDR);
    dp_x0y0->ramDI(memDI); dp_x0y0->romDI(memDI);
    dp_x0y0->ramEN(memEN); dp_x0y0->romEN(memEN);
    dp_x0y0->ramCLK(memCLK); dp_x0y0->romCLK(memCLK);
    dp_x0y0->ramRST(memRST); dp_x0y0->romRST(memRST);
    dp_x0y0->ramDO(ramDO0);
    dp_x0y0->ramWE(ramWE0);
    dp_x0y0->romDO(romDO0);
    dp_x0y0->romWE(romWE0);

    dp_x1y0->ramADDR(memADDR); dp_x1y0->romADDR(memADDR);
    dp_x1y0->ramDI(memDI); dp_x1y0->romDI(memDI);
    dp_x1y0->ramEN(memEN); dp_x1y0->romEN(memEN);
    dp_x1y0->ramCLK(memCLK); dp_x1y0->romCLK(memCLK);
    dp_x1y0->ramRST(memRST); dp_x1y0->romRST(memRST);
    dp_x1y0->ramDO(ramDO1);
    dp_x1y0->ramWE(ramWE1);
    dp_x1y0->romDO(romDO1);
    dp_x1y0->romWE(romWE1);

    dp_x0y1->ramADDR(memADDR); dp_x0y1->romADDR(memADDR);
    dp_x0y1->ramDI(memDI); dp_x0y1->romDI(memDI);
    dp_x0y1->ramEN(memEN); dp_x0y1->romEN(memEN);
    dp_x0y1->ramCLK(memCLK); dp_x0y1->romCLK(memCLK);
    dp_x0y1->ramRST(memRST); dp_x0y1->romRST(memRST);
    dp_x0y1->ramDO(ramDO2);
    dp_x0y1->ramWE(ramWE2);
    dp_x0y1->romDO(romDO2);
    dp_x0y1->romWE(romWE2);

    dp_x1y1->ramADDR(memADDR); dp_x1y1->romADDR(memADDR);
    dp_x1y1->ramDI(memDI); dp_x1y1->romDI(memDI);
    dp_x1y1->ramEN(memEN); dp_x1y1->romEN(memEN);
    dp_x1y1->ramCLK(memCLK); dp_x1y1->romCLK(memCLK);
    dp_x1y1->ramRST(memRST); dp_x1y1->romRST(memRST);
    dp_x1y1->ramDO(ramDO3);
    dp_x1y1->ramWE(ramWE3);
    dp_x1y1->romDO(romDO3);
    dp_x1y1->romWE(romWE3);

    dp_x0y2->ramADDR(memADDR); dp_x0y2->romADDR(memADDR);
    dp_x0y2->ramDI(memDI); dp_x0y2->romDI(memDI);
    dp_x0y2->ramEN(memEN); dp_x0y2->romEN(memEN);
    dp_x0y2->ramCLK(memCLK); dp_x0y2->romCLK(memCLK);
    dp_x0y2->ramRST(memRST); dp_x0y2->romRST(memRST);
    dp_x0y2->ramDO(ramDO4);
    dp_x0y2->ramWE(ramWE4);
    dp_x0y2->romDO(romDO4);
    dp_x0y2->romWE(romWE4);

    dp_x1y2->ramADDR(memADDR); dp_x1y2->romADDR(memADDR);
    dp_x1y2->ramDI(memDI); dp_x1y2->romDI(memDI);
    dp_x1y2->ramEN(memEN); dp_x1y2->romEN(memEN);
    dp_x1y2->ramCLK(memCLK); dp_x1y2->romCLK(memCLK);
    dp_x1y2->ramRST(memRST); dp_x1y2->romRST(memRST);
    dp_x1y2->ramDO(ramDO5);
    dp_x1y2->ramWE(ramWE5);
    dp_x1y2->romDO(romDO5);
    dp_x1y2->romWE(romWE5);

#ifdef USEXRAM
    wrapper->xADDR(xADDR);
    wrapper->xCLK(xCLK);
    wrapper->xDO0(xDO0);
    wrapper->xWE0(xWE0);
    wrapper->xDO1(xDO1);
    wrapper->xWE1(xWE1);
    wrapper->xDO2(xDO2);
    wrapper->xWE2(xWE2);
    wrapper->xDO3(xDO3);
    wrapper->xWE3(xWE3);
    wrapper->xDO4(xDO4);
    wrapper->xWE4(xWE4);
    wrapper->xDO5(xDO5);
    wrapper->xWE5(xWE5);
    dp_x0y0->xADDR(xADDR);
    dp_x0y0->xCLK(xCLK);
    dp_x0y0->xDO(xDO0);
    dp_x0y0->xWE(xWE0);

    dp_x1y0->xADDR(xADDR);
    dp_x1y0->xCLK(xCLK);
    dp_x1y0->xDO(xDO1);
    dp_x1y0->xWE(xWE1);

    dp_x0y1->xADDR(xADDR);
    dp_x0y1->xCLK(xCLK);
    dp_x0y1->xDO(xDO2);
    dp_x0y1->xWE(xWE2);

    dp_x1y1->xADDR(xADDR);
    dp_x1y1->xCLK(xCLK);
    dp_x1y1->xDO(xDO3);
    dp_x1y1->xWE(xWE3);

    dp_x0y2->xADDR(xADDR);
    dp_x0y2->xCLK(xCLK);
    dp_x0y2->xDO(xDO4);
    dp_x0y2->xWE(xWE4);

    dp_x1y2->xADDR(xADDR);
    dp_x1y2->xCLK(xCLK);
    dp_x1y2->xDO(xDO5);
    dp_x1y2->xWE(xWE5);

#endif
    network2x3->clk(MIPSCLK); network2x3->rst(reset);
    network2x3->x0y0din(x0y0din);
    network2x3->x0y0dout(x0y0dout);
    network2x3->x0y0req_net(x0y0req_net);
    network2x3->x0y0ack_net(x0y0ack_net);
    network2x3->x0y0ack_dp(x0y0ack_dp);
    network2x3->x0y0req_dp(x0y0req_dp);
    network2x3->x1y0din(x1y0din);
    network2x3->x1y0dout(x1y0dout);
    network2x3->x1y0req_net(x1y0req_net);
    network2x3->x1y0ack_net(x1y0ack_net);
    network2x3->x1y0ack_dp(x1y0ack_dp);
    network2x3->x1y0req_dp(x1y0req_dp);
    network2x3->x0y1din(x0y1din);
    network2x3->x0y1dout(x0y1dout);
    network2x3->x0y1req_net(x0y1req_net);
    network2x3->x0y1ack_net(x0y1ack_net);
    network2x3->x0y1ack_dp(x0y1ack_dp);
    network2x3->x0y1req_dp(x0y1req_dp);
    network2x3->x1y1din(x1y1din);
    network2x3->x1y1dout(x1y1dout);
    network2x3->x1y1req_net(x1y1req_net);
    network2x3->x1y1ack_net(x1y1ack_net);
    network2x3->x1y1ack_dp(x1y1ack_dp);
    network2x3->x1y1req_dp(x1y1req_dp);
    network2x3->x0y2din(x0y2din);
    network2x3->x0y2dout(x0y2dout);
    network2x3->x0y2req_net(x0y2req_net);
    network2x3->x0y2ack_net(x0y2ack_net);
    network2x3->x0y2ack_dp(x0y2ack_dp);
    network2x3->x0y2req_dp(x0y2req_dp);
    network2x3->x1y2din(x1y2din);
    network2x3->x1y2dout(x1y2dout);
    network2x3->x1y2req_net(x1y2req_net);
    network2x3->x1y2ack_net(x1y2ack_net);
    network2x3->x1y2ack_dp(x1y2ack_dp);
    network2x3->x1y2req_dp(x1y2req_dp);

    dp_x0y0->clock(MIPSCLK); dp_x0y0->reset(reset); dp_x0y0->enable(enable0);
    dp_x0y0->data_out(x0y0din);
    dp_x0y0->data_in(x0y0dout);
    dp_x0y0->req_out(x0y0req_net);
    dp_x0y0->ack_in(x0y0ack_net);
    dp_x0y0->ack_out(x0y0ack_dp);
    dp_x0y0->req_in(x0y0req_dp);

    dp_x1y0->clock(MIPSCLK); dp_x1y0->reset(reset); dp_x1y0->enable(enable1);
    dp_x1y0->data_out(x1y0din);
    dp_x1y0->data_in(x1y0dout);
    dp_x1y0->req_out(x1y0req_net);
    dp_x1y0->ack_in(x1y0ack_net);
    dp_x1y0->ack_out(x1y0ack_dp);
    dp_x1y0->req_in(x1y0req_dp);

    dp_x0y1->clock(MIPSCLK); dp_x0y1->reset(reset); dp_x0y1->enable(enable2);
    dp_x0y1->data_out(x0y1din);
    dp_x0y1->data_in(x0y1dout);
    dp_x0y1->req_out(x0y1req_net);
    dp_x0y1->ack_in(x0y1ack_net);
    dp_x0y1->ack_out(x0y1ack_dp);
    dp_x0y1->req_in(x0y1req_dp);

    dp_x1y1->clock(MIPSCLK); dp_x1y1->reset(reset); dp_x1y1->enable(enable3);
    dp_x1y1->data_out(x1y1din);
    dp_x1y1->data_in(x1y1dout);
    dp_x1y1->req_out(x1y1req_net);
    dp_x1y1->ack_in(x1y1ack_net);
    dp_x1y1->ack_out(x1y1ack_dp);
    dp_x1y1->req_in(x1y1req_dp);

    dp_x0y2->clock(MIPSCLK); dp_x0y2->reset(reset); dp_x0y2->enable(enable4);
    dp_x0y2->data_out(x0y2din);
    dp_x0y2->data_in(x0y2dout);
    dp_x0y2->req_out(x0y2req_net);
    dp_x0y2->ack_in(x0y2ack_net);
    dp_x0y2->ack_out(x0y2ack_dp);
    dp_x0y2->req_in(x0y2req_dp);

    dp_x1y2->clock(MIPSCLK); dp_x1y2->reset(reset); dp_x1y2->enable(enable5);
    dp_x1y2->data_out(x1y2din);
    dp_x1y2->data_in(x1y2dout);
    dp_x1y2->req_out(x1y2req_net);
    dp_x1y2->ack_in(x1y2ack_net);
    dp_x1y2->ack_out(x1y2ack_dp);
    dp_x1y2->req_in(x1y2req_dp);

    dp_x0y0->bus_pc(pc0); wrapper->pc0(pc0);
    dp_x1y0->bus_pc(pc1); wrapper->pc1(pc1);
    dp_x0y1->bus_pc(pc2); wrapper->pc2(pc2);
    dp_x1y1->bus_pc(pc3); wrapper->pc3(pc3);
    dp_x0y2->bus_pc(pc4); wrapper->pc4(pc4);
    dp_x1y2->bus_pc(pc5); wrapper->pc5(pc5);
  }
};