netmemif.h

改进的基于6个mips核的NOC网络

#ifndef NETMEMIF_H_INCLUDED
#define NETMEMIF_H_INCLUDED

#include <systemc.h>

SC_MODULE(NETMEM_IF)
{
  sc_in< bool > clk, rst;
  
  // network interface
  sc_in< sc_bv<FLIT_LEN> > data_in;
  sc_in< bool > req_in, ack_in;

  sc_out< sc_bv<FLIT_LEN> > data_out;
  sc_out< bool > req_out, ack_out;

  // memory interface
  sc_out< sc_uint<32> > mem_addr;
  sc_out< sc_int<16> > mem_din;
  sc_out< bool > mem_wh, mem_wl, mem_wb, mem_r;
  sc_in< sc_int<32> > mem_dout;


  // buffers for addresses for write and read
  
  sc_signal< sc_int<32> > write_address, read_address;
  // write enables for high/low parts of address
  sc_signal< bool > wr_wah,wr_wal,wr_rah,wr_ral;
  // increment write/read address (by 4)
  sc_signal< bool > inc_wa, inc_ra;
  
  
  // couters for read and write operations
  
  sc_signal< sc_int<8> > read_counter, write_counter;
  // write counter contents
  sc_signal< bool > wr_rc,wr_wc;
  // decrement counter (by 1)
  sc_signal< bool > dec_rc,dec_wc;  
  
  // return address 
  sc_signal< sc_uint<16> > read_return_address, write_return_address;
  sc_signal< bool > wr_rra, wr_wra;
  
  // byte to write to memory
  sc_signal< sc_int<8> > byte;
  sc_signal< bool > wr_b;
  
  // memory output buffer
  sc_signal< sc_int<32> > memory_buffer;
  sc_signal< bool > wr_mb;

  // buffer for requested operation
  sc_signal< sc_uint<2> > operation;
  sc_signal< bool > wr_op;
  
  void buffers_process();
  
  
  enum flit_type { HEADER, OP, RETADDR, ADDRH, ADDRL, DATAH, DATAL };
  
  // main control FSM - receives a whole packet and 
  // writes data (if its write request), or starts sending process
  // if its read request
  enum rcv_state { RCV, RCV_WAIT_REQ, WAIT_READ };
#ifdef VERILOG
  sc_signal< rcv_state > rcv_current_state, rcv_next_state;
  sc_signal< flit_type > rcv_current_flit, rcv_next_flit;
#else
  sc_signal< unsigned > rcv_current_state, rcv_next_state;
  sc_signal< unsigned > rcv_current_flit, rcv_next_flit;
#endif  
  void rcv_change_state();
  void rcv_logic();
  
  // sending FSM
  enum send_state { SEND, SEND_WAIT_ACK, WAIT_READ };
#ifdef VERILOG
  sc_signal< send_state > send_current_state, send_next_state;
  sc_signal< flit_type > send_current_flit, send_next_flit;
#else
  sc_signal< unsigned > send_current_state, send_next_state;
  sc_signal< unsigned > send_current_flit, send_next_flit;
#endif  
  void send_change_state();
  void send_logic();
  
  sc_signal< bool > start_sending;
  sc_signal< bool > writing;
  sc_signal< bool > sending;
  
  
  void memory_input();
  
  SC_CTOR(NETMEM_IF)
	{
	  SC_METHOD(buffers_process);
	  sensitive_pos << clk;
	  
	  SC_METHOD(rcv_change_state);
	  sensitive_pos << clk;

	  SC_METHOD(rcv_logic);
	  sensitive_pos << rcv_current_state << rcv_current_flit 
					<< data_in << req_in << write_counter
					<< sending;

	  SC_METHOD(send_change_state);
	  sensitive_pos << clk;

	  SC_METHOD(send_logic);
	  sensitive_pos << send_current_state << send_current_flit 
					<< start_sending << writing << read_counter
					<< ack_in;

	  SC_METHOD(memory_input);
	  sensitive << mem_r << mem_wb 
				<< data_in << byte << write_address << read_address 
				<< read_return_address << write_return_address;
	}
}

#endif