benif_network3x3.h

改进的基于6个mips核的NOC网络

    dp_x0y0->ramDO(ramDO0);
    dp_x0y0->ramWE(ramWE0);
    dp_x0y0->romDO(romDO0);
    dp_x0y0->romWE(romWE0);

    dp_x1y0->ramADDR(memADDR); dp_x1y0->romADDR(memADDR);
    dp_x1y0->ramDI(memDI); dp_x1y0->romDI(memDI);
    dp_x1y0->ramEN(memEN); dp_x1y0->romEN(memEN);
    dp_x1y0->ramCLK(memCLK); dp_x1y0->romCLK(memCLK);
    dp_x1y0->ramRST(memRST); dp_x1y0->romRST(memRST);
    dp_x1y0->ramDO(ramDO1);
    dp_x1y0->ramWE(ramWE1);
    dp_x1y0->romDO(romDO1);
    dp_x1y0->romWE(romWE1);

    dp_x2y0->ramADDR(memADDR); dp_x2y0->romADDR(memADDR);
    dp_x2y0->ramDI(memDI); dp_x2y0->romDI(memDI);
    dp_x2y0->ramEN(memEN); dp_x2y0->romEN(memEN);
    dp_x2y0->ramCLK(memCLK); dp_x2y0->romCLK(memCLK);
    dp_x2y0->ramRST(memRST); dp_x2y0->romRST(memRST);
    dp_x2y0->ramDO(ramDO2);
    dp_x2y0->ramWE(ramWE2);
    dp_x2y0->romDO(romDO2);
    dp_x2y0->romWE(romWE2);

    dp_x0y1->ramADDR(memADDR); dp_x0y1->romADDR(memADDR);
    dp_x0y1->ramDI(memDI); dp_x0y1->romDI(memDI);
    dp_x0y1->ramEN(memEN); dp_x0y1->romEN(memEN);
    dp_x0y1->ramCLK(memCLK); dp_x0y1->romCLK(memCLK);
    dp_x0y1->ramRST(memRST); dp_x0y1->romRST(memRST);
    dp_x0y1->ramDO(ramDO3);
    dp_x0y1->ramWE(ramWE3);
    dp_x0y1->romDO(romDO3);
    dp_x0y1->romWE(romWE3);

    dp_x1y1->ramADDR(memADDR); dp_x1y1->romADDR(memADDR);
    dp_x1y1->ramDI(memDI); dp_x1y1->romDI(memDI);
    dp_x1y1->ramEN(memEN); dp_x1y1->romEN(memEN);
    dp_x1y1->ramCLK(memCLK); dp_x1y1->romCLK(memCLK);
    dp_x1y1->ramRST(memRST); dp_x1y1->romRST(memRST);
    dp_x1y1->ramDO(ramDO4);
    dp_x1y1->ramWE(ramWE4);
    dp_x1y1->romDO(romDO4);
    dp_x1y1->romWE(romWE4);

    dp_x2y1->ramADDR(memADDR); dp_x2y1->romADDR(memADDR);
    dp_x2y1->ramDI(memDI); dp_x2y1->romDI(memDI);
    dp_x2y1->ramEN(memEN); dp_x2y1->romEN(memEN);
    dp_x2y1->ramCLK(memCLK); dp_x2y1->romCLK(memCLK);
    dp_x2y1->ramRST(memRST); dp_x2y1->romRST(memRST);
    dp_x2y1->ramDO(ramDO5);
    dp_x2y1->ramWE(ramWE5);
    dp_x2y1->romDO(romDO5);
    dp_x2y1->romWE(romWE5);

    dp_x0y2->ramADDR(memADDR); dp_x0y2->romADDR(memADDR);
    dp_x0y2->ramDI(memDI); dp_x0y2->romDI(memDI);
    dp_x0y2->ramEN(memEN); dp_x0y2->romEN(memEN);
    dp_x0y2->ramCLK(memCLK); dp_x0y2->romCLK(memCLK);
    dp_x0y2->ramRST(memRST); dp_x0y2->romRST(memRST);
    dp_x0y2->ramDO(ramDO6);
    dp_x0y2->ramWE(ramWE6);
    dp_x0y2->romDO(romDO6);
    dp_x0y2->romWE(romWE6);

    dp_x1y2->ramADDR(memADDR); dp_x1y2->romADDR(memADDR);
    dp_x1y2->ramDI(memDI); dp_x1y2->romDI(memDI);
    dp_x1y2->ramEN(memEN); dp_x1y2->romEN(memEN);
    dp_x1y2->ramCLK(memCLK); dp_x1y2->romCLK(memCLK);
    dp_x1y2->ramRST(memRST); dp_x1y2->romRST(memRST);
    dp_x1y2->ramDO(ramDO7);
    dp_x1y2->ramWE(ramWE7);
    dp_x1y2->romDO(romDO7);
    dp_x1y2->romWE(romWE7);

    dp_x2y2->ramADDR(memADDR); dp_x2y2->romADDR(memADDR);
    dp_x2y2->ramDI(memDI); dp_x2y2->romDI(memDI);
    dp_x2y2->ramEN(memEN); dp_x2y2->romEN(memEN);
    dp_x2y2->ramCLK(memCLK); dp_x2y2->romCLK(memCLK);
    dp_x2y2->ramRST(memRST); dp_x2y2->romRST(memRST);
    dp_x2y2->ramDO(ramDO8);
    dp_x2y2->ramWE(ramWE8);
    dp_x2y2->romDO(romDO8);
    dp_x2y2->romWE(romWE8);

#ifdef USEXRAM
    wrapper->xADDR(xADDR);
    wrapper->xCLK(xCLK);
    wrapper->xDO0(xDO0);
    wrapper->xWE0(xWE0);
    wrapper->xDO1(xDO1);
    wrapper->xWE1(xWE1);
    wrapper->xDO2(xDO2);
    wrapper->xWE2(xWE2);
    wrapper->xDO3(xDO3);
    wrapper->xWE3(xWE3);
    wrapper->xDO4(xDO4);
    wrapper->xWE4(xWE4);
    wrapper->xDO5(xDO5);
    wrapper->xWE5(xWE5);
    wrapper->xDO6(xDO6);
    wrapper->xWE6(xWE6);
    wrapper->xDO7(xDO7);
    wrapper->xWE7(xWE7);
    wrapper->xDO8(xDO8);
    wrapper->xWE8(xWE8);
    dp_x0y0->xADDR(xADDR);
    dp_x0y0->xCLK(xCLK);
    dp_x0y0->xDO(xDO0);
    dp_x0y0->xWE(xWE0);

    dp_x1y0->xADDR(xADDR);
    dp_x1y0->xCLK(xCLK);
    dp_x1y0->xDO(xDO1);
    dp_x1y0->xWE(xWE1);

    dp_x2y0->xADDR(xADDR);
    dp_x2y0->xCLK(xCLK);
    dp_x2y0->xDO(xDO2);
    dp_x2y0->xWE(xWE2);

    dp_x0y1->xADDR(xADDR);
    dp_x0y1->xCLK(xCLK);
    dp_x0y1->xDO(xDO3);
    dp_x0y1->xWE(xWE3);

    dp_x1y1->xADDR(xADDR);
    dp_x1y1->xCLK(xCLK);
    dp_x1y1->xDO(xDO4);
    dp_x1y1->xWE(xWE4);

    dp_x2y1->xADDR(xADDR);
    dp_x2y1->xCLK(xCLK);
    dp_x2y1->xDO(xDO5);
    dp_x2y1->xWE(xWE5);

    dp_x0y2->xADDR(xADDR);
    dp_x0y2->xCLK(xCLK);
    dp_x0y2->xDO(xDO6);
    dp_x0y2->xWE(xWE6);

    dp_x1y2->xADDR(xADDR);
    dp_x1y2->xCLK(xCLK);
    dp_x1y2->xDO(xDO7);
    dp_x1y2->xWE(xWE7);

    dp_x2y2->xADDR(xADDR);
    dp_x2y2->xCLK(xCLK);
    dp_x2y2->xDO(xDO8);
    dp_x2y2->xWE(xWE8);

#endif
    network3x3->clk(MIPSCLK); network3x3->rst(reset);
    network3x3->x0y0din(x0y0din);
    network3x3->x0y0dout(x0y0dout);
    network3x3->x0y0req_net(x0y0req_net);
    network3x3->x0y0ack_net(x0y0ack_net);
    network3x3->x0y0ack_dp(x0y0ack_dp);
    network3x3->x0y0req_dp(x0y0req_dp);
    network3x3->x1y0din(x1y0din);
    network3x3->x1y0dout(x1y0dout);
    network3x3->x1y0req_net(x1y0req_net);
    network3x3->x1y0ack_net(x1y0ack_net);
    network3x3->x1y0ack_dp(x1y0ack_dp);
    network3x3->x1y0req_dp(x1y0req_dp);
    network3x3->x2y0din(x2y0din);
    network3x3->x2y0dout(x2y0dout);
    network3x3->x2y0req_net(x2y0req_net);
    network3x3->x2y0ack_net(x2y0ack_net);
    network3x3->x2y0ack_dp(x2y0ack_dp);
    network3x3->x2y0req_dp(x2y0req_dp);
    network3x3->x0y1din(x0y1din);
    network3x3->x0y1dout(x0y1dout);
    network3x3->x0y1req_net(x0y1req_net);
    network3x3->x0y1ack_net(x0y1ack_net);
    network3x3->x0y1ack_dp(x0y1ack_dp);
    network3x3->x0y1req_dp(x0y1req_dp);
    network3x3->x1y1din(x1y1din);
    network3x3->x1y1dout(x1y1dout);
    network3x3->x1y1req_net(x1y1req_net);
    network3x3->x1y1ack_net(x1y1ack_net);
    network3x3->x1y1ack_dp(x1y1ack_dp);
    network3x3->x1y1req_dp(x1y1req_dp);
    network3x3->x2y1din(x2y1din);
    network3x3->x2y1dout(x2y1dout);
    network3x3->x2y1req_net(x2y1req_net);
    network3x3->x2y1ack_net(x2y1ack_net);
    network3x3->x2y1ack_dp(x2y1ack_dp);
    network3x3->x2y1req_dp(x2y1req_dp);
    network3x3->x0y2din(x0y2din);
    network3x3->x0y2dout(x0y2dout);
    network3x3->x0y2req_net(x0y2req_net);
    network3x3->x0y2ack_net(x0y2ack_net);
    network3x3->x0y2ack_dp(x0y2ack_dp);
    network3x3->x0y2req_dp(x0y2req_dp);
    network3x3->x1y2din(x1y2din);
    network3x3->x1y2dout(x1y2dout);
    network3x3->x1y2req_net(x1y2req_net);
    network3x3->x1y2ack_net(x1y2ack_net);
    network3x3->x1y2ack_dp(x1y2ack_dp);
    network3x3->x1y2req_dp(x1y2req_dp);
    network3x3->x2y2din(x2y2din);
    network3x3->x2y2dout(x2y2dout);
    network3x3->x2y2req_net(x2y2req_net);
    network3x3->x2y2ack_net(x2y2ack_net);
    network3x3->x2y2ack_dp(x2y2ack_dp);
    network3x3->x2y2req_dp(x2y2req_dp);

    dp_x0y0->clock(MIPSCLK); dp_x0y0->reset(reset); dp_x0y0->enable(enable0);
    dp_x0y0->data_out(x0y0din);
    dp_x0y0->data_in(x0y0dout);
    dp_x0y0->req_out(x0y0req_net);
    dp_x0y0->ack_in(x0y0ack_net);
    dp_x0y0->ack_out(x0y0ack_dp);
    dp_x0y0->req_in(x0y0req_dp);

    dp_x1y0->clock(MIPSCLK); dp_x1y0->reset(reset); dp_x1y0->enable(enable1);
    dp_x1y0->data_out(x1y0din);
    dp_x1y0->data_in(x1y0dout);
    dp_x1y0->req_out(x1y0req_net);
    dp_x1y0->ack_in(x1y0ack_net);
    dp_x1y0->ack_out(x1y0ack_dp);
    dp_x1y0->req_in(x1y0req_dp);

    dp_x2y0->clock(MIPSCLK); dp_x2y0->reset(reset); dp_x2y0->enable(enable2);
    dp_x2y0->data_out(x2y0din);
    dp_x2y0->data_in(x2y0dout);
    dp_x2y0->req_out(x2y0req_net);
    dp_x2y0->ack_in(x2y0ack_net);
    dp_x2y0->ack_out(x2y0ack_dp);
    dp_x2y0->req_in(x2y0req_dp);

    dp_x0y1->clock(MIPSCLK); dp_x0y1->reset(reset); dp_x0y1->enable(enable3);
    dp_x0y1->data_out(x0y1din);
    dp_x0y1->data_in(x0y1dout);
    dp_x0y1->req_out(x0y1req_net);
    dp_x0y1->ack_in(x0y1ack_net);
    dp_x0y1->ack_out(x0y1ack_dp);
    dp_x0y1->req_in(x0y1req_dp);

    dp_x1y1->clock(MIPSCLK); dp_x1y1->reset(reset); dp_x1y1->enable(enable4);
    dp_x1y1->data_out(x1y1din);
    dp_x1y1->data_in(x1y1dout);
    dp_x1y1->req_out(x1y1req_net);
    dp_x1y1->ack_in(x1y1ack_net);
    dp_x1y1->ack_out(x1y1ack_dp);
    dp_x1y1->req_in(x1y1req_dp);

    dp_x2y1->clock(MIPSCLK); dp_x2y1->reset(reset); dp_x2y1->enable(enable5);
    dp_x2y1->data_out(x2y1din);
    dp_x2y1->data_in(x2y1dout);
    dp_x2y1->req_out(x2y1req_net);
    dp_x2y1->ack_in(x2y1ack_net);
    dp_x2y1->ack_out(x2y1ack_dp);
    dp_x2y1->req_in(x2y1req_dp);

    dp_x0y2->clock(MIPSCLK); dp_x0y2->reset(reset); dp_x0y2->enable(enable6);
    dp_x0y2->data_out(x0y2din);
    dp_x0y2->data_in(x0y2dout);
    dp_x0y2->req_out(x0y2req_net);
    dp_x0y2->ack_in(x0y2ack_net);
    dp_x0y2->ack_out(x0y2ack_dp);
    dp_x0y2->req_in(x0y2req_dp);

    dp_x1y2->clock(MIPSCLK); dp_x1y2->reset(reset); dp_x1y2->enable(enable7);
    dp_x1y2->data_out(x1y2din);
    dp_x1y2->data_in(x1y2dout);
    dp_x1y2->req_out(x1y2req_net);
    dp_x1y2->ack_in(x1y2ack_net);
    dp_x1y2->ack_out(x1y2ack_dp);
    dp_x1y2->req_in(x1y2req_dp);

    dp_x2y2->clock(MIPSCLK); dp_x2y2->reset(reset); dp_x2y2->enable(enable8);
    dp_x2y2->data_out(x2y2din);
    dp_x2y2->data_in(x2y2dout);
    dp_x2y2->req_out(x2y2req_net);
    dp_x2y2->ack_in(x2y2ack_net);
    dp_x2y2->ack_out(x2y2ack_dp);
    dp_x2y2->req_in(x2y2req_dp);

    dp_x0y0->bus_pc(pc0); wrapper->pc0(pc0);
    dp_x1y0->bus_pc(pc1); wrapper->pc1(pc1);
    dp_x2y0->bus_pc(pc2); wrapper->pc2(pc2);
    dp_x0y1->bus_pc(pc3); wrapper->pc3(pc3);
    dp_x1y1->bus_pc(pc4); wrapper->pc4(pc4);
    dp_x2y1->bus_pc(pc5); wrapper->pc5(pc5);
    dp_x0y2->bus_pc(pc6); wrapper->pc6(pc6);
    dp_x1y2->bus_pc(pc7); wrapper->pc7(pc7);
    dp_x2y2->bus_pc(pc8); wrapper->pc8(pc8);
  }
};