benif_network3x3.h

改进的基于6个mips核的NOC网络

#include <systemc.h>
#include "netmips.h"
#include "network3x3.h"

SC_MODULE(BENIF_NET_WRAPPER)
{
  sc_in< bool > IFCLK;
  sc_in< bool > WRITE_STROBE;
  sc_in< bool > READ_STROBE;
  sc_in< bool > DMA_ENABLE;
  sc_in< bool > DMA_DIRECTION;
  sc_in< bool > DMA_RDY;
  sc_in< bool > DMA_DATA_AVAILABLE;
  sc_in< bool > RST;
  sc_in< bool > SYNC_RESET;
  sc_in< bool > DMA_RESET;

  sc_in< sc_uint<31> > ADDRESS;
  sc_inout_rv< 32 > DATA;

  sc_inout_rv< 32 > DMA_DATA;
  sc_in< sc_uint<32> > COUNT;
  sc_in< sc_uint<4> > DMA_SEL;

  sc_out< bool > DMA_WEN;
  sc_out< bool > DMA_REN;
  sc_out< bool > INT;

  sc_out< sc_bv<4> > LEDS;

  sc_out<sc_uint<32> > memADDR;
  sc_out<sc_int<32> > memDI;
  sc_out<bool> memEN;
  sc_out<bool> memCLK;
  sc_out<bool> memRST;
  sc_in<sc_int<32> > ramDO0,romDO0,ramDO1,romDO1,ramDO2,romDO2,ramDO3,romDO3,ramDO4,romDO4,ramDO5,romDO5,ramDO6,romDO6,ramDO7,romDO7,ramDO8,romDO8;
  sc_out<bool> ramWE0,romWE0,ramWE1,romWE1,ramWE2,romWE2,ramWE3,romWE3,ramWE4,romWE4,ramWE5,romWE5,ramWE6,romWE6,ramWE7,romWE7,ramWE8,romWE8;
  sc_in<sc_bv<32> > pc0,pc1,pc2,pc3,pc4,pc5,pc6,pc7,pc8;
  sc_out<bool> enable0,enable1,enable2,enable3,enable4,enable5,enable6,enable7,enable8;
  sc_out<bool> reset;

#ifdef USEXRAM
  sc_out<sc_uint<32> > xADDR;
  sc_out<bool> xCLK;
  sc_in<sc_int<32> > xDO0,xDO1,xDO2,xDO3,xDO4,xDO5,xDO6,xDO7,xDO8;
  sc_out<bool> xWE0,xWE1,xWE2,xWE3,xWE4,xWE5,xWE6,xWE7,xWE8;
#endif

  sc_signal< sc_uint<32> > addr;
  sc_signal< sc_uint<32> > memsel;
  sc_signal< sc_uint<25> > cnt;
  
  sc_signal< sc_uint<32> > control;
  
  void logic();
  void count();
  void register_write();
  void register_read();
  void memory_input();
  
  SC_CTOR(BENIF_NET_WRAPPER)
  {
    SC_METHOD(logic);
    sensitive << IFCLK << WRITE_STROBE << READ_STROBE << DMA_ENABLE 
              << DMA_DIRECTION << DMA_RDY << DMA_DATA_AVAILABLE
              << RST << SYNC_RESET << DMA_RESET
              << ADDRESS << DATA
              << DMA_DATA << COUNT << DMA_SEL
              << control << addr << memsel << cnt;

    SC_METHOD(memory_input);
    sensitive << IFCLK << DATA << addr << memsel << ADDRESS << WRITE_STROBE << control;

    SC_METHOD(count);
    sensitive_pos << IFCLK << RST;
    
    SC_METHOD(register_write);
    sensitive_pos << IFCLK << RST;
    
    SC_METHOD(register_read);
    sensitive << READ_STROBE << ADDRESS << addr << memsel;
  sensitive << pc0 << pc1 << pc2 << pc3 << pc4 << pc5 << pc6 << pc7 << pc8;
  sensitive << ramDO0 << romDO0 << ramDO1 << romDO1 << ramDO2 << romDO2 << ramDO3 << romDO3 << ramDO4 << romDO4 << ramDO5 << romDO5 << ramDO6 << romDO6 << ramDO7 << romDO7 << ramDO8 << romDO8;
#ifdef USEXRAM
  sensitive << xDO0 << xDO1 << xDO2 << xDO3 << xDO4 << xDO5 << xDO6 << xDO7 << xDO8;
#endif
  }
};

SC_MODULE(BENIF_NET)
{
  NETWORK3x3 *network3x3;
  NETmMIPS *dp_x0y0;
  NETmMIPS *dp_x1y0;
  NETmMIPS *dp_x2y0;
  NETmMIPS *dp_x0y1;
  NETmMIPS *dp_x1y1;
  NETmMIPS *dp_x2y1;
  NETmMIPS *dp_x0y2;
  NETmMIPS *dp_x1y2;
  NETmMIPS *dp_x2y2;
  BENIF_NET_WRAPPER *wrapper;

  
  sc_in<bool>   MIPSCLK;
  
  sc_in< bool > IFCLK;
  sc_in< bool > WRITE_STROBE;
  sc_in< bool > READ_STROBE;
  sc_in< bool > DMA_ENABLE;
  sc_in< bool > DMA_DIRECTION;
  sc_in< bool > DMA_RDY;
  sc_in< bool > DMA_DATA_AVAILABLE;
  sc_in< bool > RST;
  sc_in< bool > SYNC_RESET;
  sc_in< bool > DMA_RESET;

  sc_in< sc_uint<31> > ADDRESS;
  sc_inout_rv< 32 > DATA;
  sc_inout_rv< 32 > DMA_DATA;
  sc_in< sc_uint<32> > COUNT;
  sc_in< sc_uint<4> > DMA_SEL;

  sc_out< bool > DMA_WEN;
  sc_out< bool > DMA_REN;
  sc_out< bool > INT;
  sc_out< sc_bv<4> > LEDS;

  sc_signal<sc_uint<32> > memADDR;
  sc_signal<sc_int<32> > memDI;
  sc_signal<bool> memEN;
  sc_signal<bool> memCLK;
  sc_signal<bool> memRST;

  sc_signal<sc_int<32> > ramDO0,romDO0,ramDO1,romDO1,ramDO2,romDO2,ramDO3,romDO3,ramDO4,romDO4,ramDO5,romDO5,ramDO6,romDO6,ramDO7,romDO7,ramDO8,romDO8;
  sc_signal<bool> ramWE0,romWE0,ramWE1,romWE1,ramWE2,romWE2,ramWE3,romWE3,ramWE4,romWE4,ramWE5,romWE5,ramWE6,romWE6,ramWE7,romWE7,ramWE8,romWE8;
  sc_signal<sc_bv<32> > pc0,pc1,pc2,pc3,pc4,pc5,pc6,pc7,pc8;
  sc_signal<bool> enable0,enable1,enable2,enable3,enable4,enable5,enable6,enable7,enable8;
  sc_signal<bool> reset;

#ifdef USEXRAM
  sc_signal<sc_uint<32> > xADDR;
  sc_signal<bool> xCLK;
  sc_signal<sc_int<32> > xDO0,xDO1,xDO2,xDO3,xDO4,xDO5,xDO6,xDO7,xDO8;
  sc_signal<bool> xWE0,xWE1,xWE2,xWE3,xWE4,xWE5,xWE6,xWE7,xWE8;
#endif
  sc_signal< sc_bv<FLIT_LEN> > x0y0din;
  sc_signal< sc_bv<FLIT_LEN> > x0y0dout;
  sc_signal<bool> x0y0req_net;
  sc_signal<bool> x0y0ack_net;
  sc_signal<bool> x0y0ack_dp;
  sc_signal<bool> x0y0req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x1y0din;
  sc_signal< sc_bv<FLIT_LEN> > x1y0dout;
  sc_signal<bool> x1y0req_net;
  sc_signal<bool> x1y0ack_net;
  sc_signal<bool> x1y0ack_dp;
  sc_signal<bool> x1y0req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x2y0din;
  sc_signal< sc_bv<FLIT_LEN> > x2y0dout;
  sc_signal<bool> x2y0req_net;
  sc_signal<bool> x2y0ack_net;
  sc_signal<bool> x2y0ack_dp;
  sc_signal<bool> x2y0req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x0y1din;
  sc_signal< sc_bv<FLIT_LEN> > x0y1dout;
  sc_signal<bool> x0y1req_net;
  sc_signal<bool> x0y1ack_net;
  sc_signal<bool> x0y1ack_dp;
  sc_signal<bool> x0y1req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x1y1din;
  sc_signal< sc_bv<FLIT_LEN> > x1y1dout;
  sc_signal<bool> x1y1req_net;
  sc_signal<bool> x1y1ack_net;
  sc_signal<bool> x1y1ack_dp;
  sc_signal<bool> x1y1req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x2y1din;
  sc_signal< sc_bv<FLIT_LEN> > x2y1dout;
  sc_signal<bool> x2y1req_net;
  sc_signal<bool> x2y1ack_net;
  sc_signal<bool> x2y1ack_dp;
  sc_signal<bool> x2y1req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x0y2din;
  sc_signal< sc_bv<FLIT_LEN> > x0y2dout;
  sc_signal<bool> x0y2req_net;
  sc_signal<bool> x0y2ack_net;
  sc_signal<bool> x0y2ack_dp;
  sc_signal<bool> x0y2req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x1y2din;
  sc_signal< sc_bv<FLIT_LEN> > x1y2dout;
  sc_signal<bool> x1y2req_net;
  sc_signal<bool> x1y2ack_net;
  sc_signal<bool> x1y2ack_dp;
  sc_signal<bool> x1y2req_dp;
  sc_signal< sc_bv<FLIT_LEN> > x2y2din;
  sc_signal< sc_bv<FLIT_LEN> > x2y2dout;
  sc_signal<bool> x2y2req_net;
  sc_signal<bool> x2y2ack_net;
  sc_signal<bool> x2y2ack_dp;
  sc_signal<bool> x2y2req_dp;

  SC_CTOR(BENIF_NET)
  {
    network3x3 = new NETWORK3x3("network3x3");
    dp_x0y0 = new NETmMIPS("dp_x0y0");
    dp_x1y0 = new NETmMIPS("dp_x1y0");
    dp_x2y0 = new NETmMIPS("dp_x2y0");
    dp_x0y1 = new NETmMIPS("dp_x0y1");
    dp_x1y1 = new NETmMIPS("dp_x1y1");
    dp_x2y1 = new NETmMIPS("dp_x2y1");
    dp_x0y2 = new NETmMIPS("dp_x0y2");
    dp_x1y2 = new NETmMIPS("dp_x1y2");
    dp_x2y2 = new NETmMIPS("dp_x2y2");
    wrapper = new BENIF_NET_WRAPPER("wrapper");

    wrapper->reset(reset);
    wrapper->enable0(enable0);
    wrapper->enable1(enable1);
    wrapper->enable2(enable2);
    wrapper->enable3(enable3);
    wrapper->enable4(enable4);
    wrapper->enable5(enable5);
    wrapper->enable6(enable6);
    wrapper->enable7(enable7);
    wrapper->enable8(enable8);
    wrapper->IFCLK(IFCLK);
    wrapper->WRITE_STROBE(WRITE_STROBE);
    wrapper->READ_STROBE(READ_STROBE);
    wrapper->DMA_ENABLE(DMA_ENABLE);
    wrapper->DMA_DIRECTION(DMA_DIRECTION);
    wrapper->DMA_RDY(DMA_RDY);
    wrapper->DMA_DATA_AVAILABLE(DMA_DATA_AVAILABLE);
    wrapper->RST(RST);
    wrapper->SYNC_RESET(SYNC_RESET);
    wrapper->DMA_RESET(DMA_RESET);
    wrapper->ADDRESS(ADDRESS);
    wrapper->DATA(DATA);
    wrapper->DMA_DATA(DMA_DATA);
    wrapper->COUNT(COUNT);
    wrapper->DMA_SEL(DMA_SEL);
    wrapper->DMA_WEN(DMA_WEN);
    wrapper->DMA_REN(DMA_REN);
    wrapper->INT(INT);
    wrapper->LEDS(LEDS);

    wrapper->memADDR(memADDR);
    wrapper->memDI(memDI);
    wrapper->memEN(memEN);
    wrapper->memCLK(memCLK);
    wrapper->memRST(memRST);
    wrapper->ramDO0(ramDO0);
    wrapper->ramWE0(ramWE0);
    wrapper->romDO0(romDO0);
    wrapper->romWE0(romWE0);
    wrapper->ramDO1(ramDO1);
    wrapper->ramWE1(ramWE1);
    wrapper->romDO1(romDO1);
    wrapper->romWE1(romWE1);
    wrapper->ramDO2(ramDO2);
    wrapper->ramWE2(ramWE2);
    wrapper->romDO2(romDO2);
    wrapper->romWE2(romWE2);
    wrapper->ramDO3(ramDO3);
    wrapper->ramWE3(ramWE3);
    wrapper->romDO3(romDO3);
    wrapper->romWE3(romWE3);
    wrapper->ramDO4(ramDO4);
    wrapper->ramWE4(ramWE4);
    wrapper->romDO4(romDO4);
    wrapper->romWE4(romWE4);
    wrapper->ramDO5(ramDO5);
    wrapper->ramWE5(ramWE5);
    wrapper->romDO5(romDO5);
    wrapper->romWE5(romWE5);
    wrapper->ramDO6(ramDO6);
    wrapper->ramWE6(ramWE6);
    wrapper->romDO6(romDO6);
    wrapper->romWE6(romWE6);
    wrapper->ramDO7(ramDO7);
    wrapper->ramWE7(ramWE7);
    wrapper->romDO7(romDO7);
    wrapper->romWE7(romWE7);
    wrapper->ramDO8(ramDO8);
    wrapper->ramWE8(ramWE8);
    wrapper->romDO8(romDO8);
    wrapper->romWE8(romWE8);

    dp_x0y0->ramADDR(memADDR); dp_x0y0->romADDR(memADDR);
    dp_x0y0->ramDI(memDI); dp_x0y0->romDI(memDI);
    dp_x0y0->ramEN(memEN); dp_x0y0->romEN(memEN);
    dp_x0y0->ramCLK(memCLK); dp_x0y0->romCLK(memCLK);
    dp_x0y0->ramRST(memRST); dp_x0y0->romRST(memRST);