netmemram.h

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   netmemram.h
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   RAM based on VirtexII 16kb BlockRAMs
 *                      Uses 32 blocks of 1-bit-wide memory
 *
 */
 
#ifndef NETMEMRAM_H_INCLUDED
#define NETMEMRAM_H_INCLUDED

#include "xlxram.h"

SC_MODULE(NETMEM_RAM_WRAPPER) {
	sc_in <	sc_uint<32> > addr;
	sc_out< sc_int<32> > dout;
	sc_in< sc_int<16> > din;
	sc_in< bool > wh, wl, wb, r;
	sc_in< bool > clk;	

	sc_out<sc_uint<14> > ADDR;
	sc_out<sc_int<1> > DI00, DI01, DI02, DI03, DI04, DI05, DI06, DI07, 
	  DI08, DI09, DI10, DI11, DI12, DI13, DI14, DI15, 
	  DI16, DI17, DI18, DI19, DI20, DI21, DI22, DI23, 
	  DI24, DI25, DI26, DI27, DI28, DI29, DI30, DI31;	
	sc_out<bool> EN, CLK, SSR, WE0, WE1, WE2, WE3;
	sc_in<sc_int<1> > DO00, DO01, DO02, DO03, DO04, DO05, DO06, DO07, 
	  DO08, DO09, DO10, DO11, DO12, DO13, DO14, DO15, 
	  DO16, DO17, DO18, DO19, DO20, DO21, DO22, DO23, 
	  DO24, DO25, DO26, DO27, DO28, DO29, DO30, DO31;
	
	void in();
	void out();
	
	SC_CTOR(NETMEM_RAM_WRAPPER) {
	  
	  SC_METHOD(in);
	  sensitive << addr << din << wh << wl << wb << r << clk;
	  
	  SC_METHOD(out);
	  sensitive << DO00 << DO01 << DO02 << DO03 << DO04 << DO05 << DO06 << DO07 
				<< DO08 << DO09 << DO10 << DO11 << DO12 << DO13 << DO14 << DO15 
				<< DO16 << DO17 << DO18 << DO19 << DO20 << DO21 << DO22 << DO23 
				<< DO24 << DO25 << DO26 << DO27 << DO28 << DO29 << DO30 << DO31;

	};
	
};

// Converter for the debugging access
SC_MODULE(NETMEM_RAM_DBGWRAPPER) {

  sc_out<sc_int<32> > DO;
  sc_in<sc_uint<32> > ADDR;
  sc_in<sc_int<32> > DI;
  sc_in<bool> EN;
  sc_in<bool> CLK;
  sc_in<bool> WE;
  sc_in<bool> RST;

  sc_out<sc_uint<14> > dADDR;
  sc_out<sc_int<1> > dDI00, dDI01, dDI02, dDI03, dDI04, dDI05, dDI06, dDI07, 
	dDI08, dDI09, dDI10, dDI11, dDI12, dDI13, dDI14, dDI15, 
	dDI16, dDI17, dDI18, dDI19, dDI20, dDI21, dDI22, dDI23, 
	dDI24, dDI25, dDI26, dDI27, dDI28, dDI29, dDI30, dDI31;	
  sc_out<bool> dEN, dCLK, dSSR, dWE;
  sc_in<sc_int<1> > dDO00, dDO01, dDO02, dDO03, dDO04, dDO05, dDO06, dDO07, 
	dDO08, dDO09, dDO10, dDO11, dDO12, dDO13, dDO14, dDO15, 
	dDO16, dDO17, dDO18, dDO19, dDO20, dDO21, dDO22, dDO23, 
	dDO24, dDO25, dDO26, dDO27, dDO28, dDO29, dDO30, dDO31;

  void in();
  void out();
	
  SC_CTOR(NETMEM_RAM_DBGWRAPPER) {  
	SC_METHOD(in);
	sensitive << ADDR << DI << EN << WE << RST << CLK;
	  
	SC_METHOD(out);
	sensitive << dDO00 << dDO01 << dDO02 << dDO03 << dDO04 << dDO05 << dDO06 << dDO07 
			  << dDO08 << dDO09 << dDO10 << dDO11 << dDO12 << dDO13 << dDO14 << dDO15 
			  << dDO16 << dDO17 << dDO18 << dDO19 << dDO20 << dDO21 << dDO22 << dDO23 
			  << dDO24 << dDO25 << dDO26 << dDO27 << dDO28 << dDO29 << dDO30 << dDO31;
  };
	
};

SC_MODULE(NETMEM_RAM) {
	sc_in <	sc_uint<32> > addr;
	sc_out< sc_int<32> > dout;
	sc_in< sc_int<16> > din;
	sc_in< bool > wh, wl, wb, r;
	sc_in< bool > clk;	

	// memory bits - bram00 keeps bit at address 00, so its MSB (BIGENDIAN)
	RAMB16_S1_S1 *bram00, *bram01, *bram02, *bram03, *bram04, 
	  *bram05, *bram06, *bram07, *bram08, 
	  *bram09, *bram10, *bram11, *bram12, 
	  *bram13, *bram14, *bram15, *bram16, 
	  *bram17, *bram18, *bram19, *bram20, 
	  *bram21, *bram22, *bram23, *bram24, 
	  *bram25, *bram26, *bram27, *bram28, 
	  *bram29, *bram30, *bram31;
	NETMEM_RAM_WRAPPER *conv;
	
	sc_signal<sc_uint<14> > ADDR;
	sc_signal<sc_int<1> > DI00, DI01, DI02, DI03, DI04, DI05, DI06, DI07, 
	  DI08, DI09, DI10, DI11, DI12, DI13, DI14, DI15, 
	  DI16, DI17, DI18, DI19, DI20, DI21, DI22, DI23, 
	  DI24, DI25, DI26, DI27, DI28, DI29, DI30, DI31;	
	sc_signal<bool> EN, CLK, SSR, WE0, WE1, WE2, WE3;
	sc_signal<sc_int<1> > DO00, DO01, DO02, DO03, DO04, DO05, DO06, DO07, 
	  DO08, DO09, DO10, DO11, DO12, DO13, DO14, DO15, 
	  DO16, DO17, DO18, DO19, DO20, DO21, DO22, DO23, 
	  DO24, DO25, DO26, DO27, DO28, DO29, DO30, DO31;

	NETMEM_RAM_DBGWRAPPER *dbgconv;
	
	// independent access to the second set of ports for debugging
	
	sc_out<sc_int<32> > dbgDO;
	sc_in<sc_uint<32> > dbgADDR;
	sc_in<sc_int<32> > dbgDI;
	sc_in<bool> dbgEN;
	sc_in<bool> dbgCLK;
	sc_in<bool> dbgWE;
	sc_in<bool> dbgRST;

	sc_signal<sc_uint<14> > dADDR;
	sc_signal<sc_int<1> > dDI00, dDI01, dDI02, dDI03, dDI04, dDI05, dDI06, dDI07, 
	  dDI08, dDI09, dDI10, dDI11, dDI12, dDI13, dDI14, dDI15, 
	  dDI16, dDI17, dDI18, dDI19, dDI20, dDI21, dDI22, dDI23, 
	  dDI24, dDI25, dDI26, dDI27, dDI28, dDI29, dDI30, dDI31;	
	sc_signal<bool> dEN, dCLK, dSSR, dWE;
	sc_signal<sc_int<1> > dDO00, dDO01, dDO02, dDO03, dDO04, dDO05, dDO06, dDO07, 
	  dDO08, dDO09, dDO10, dDO11, dDO12, dDO13, dDO14, dDO15, 
	  dDO16, dDO17, dDO18, dDO19, dDO20, dDO21, dDO22, dDO23, 
	  dDO24, dDO25, dDO26, dDO27, dDO28, dDO29, dDO30, dDO31;
	
#ifndef VERILOG
	void mem_init(const char *filename, int size=65536);
	void mem_dump(const char *filename, int size=65536);
#endif

	SC_CTOR(NETMEM_RAM) {

	  bram00 = new RAMB16_S1_S1("bram00");
	  bram01 = new RAMB16_S1_S1("bram01");
	  bram02 = new RAMB16_S1_S1("bram02");
	  bram03 = new RAMB16_S1_S1("bram03");
	  bram04 = new RAMB16_S1_S1("bram04");
	  bram05 = new RAMB16_S1_S1("bram05");
	  bram06 = new RAMB16_S1_S1("bram06");
	  bram07 = new RAMB16_S1_S1("bram07");
	  bram08 = new RAMB16_S1_S1("bram08");
	  bram09 = new RAMB16_S1_S1("bram09");
	  bram10 = new RAMB16_S1_S1("bram10");
	  bram11 = new RAMB16_S1_S1("bram11");
	  bram12 = new RAMB16_S1_S1("bram12");
	  bram13 = new RAMB16_S1_S1("bram13");
	  bram14 = new RAMB16_S1_S1("bram14");
	  bram15 = new RAMB16_S1_S1("bram15");
	  bram16 = new RAMB16_S1_S1("bram16");
	  bram17 = new RAMB16_S1_S1("bram17");
	  bram18 = new RAMB16_S1_S1("bram18");
	  bram19 = new RAMB16_S1_S1("bram19");
	  bram20 = new RAMB16_S1_S1("bram20");
	  bram21 = new RAMB16_S1_S1("bram21");
	  bram22 = new RAMB16_S1_S1("bram22");
	  bram23 = new RAMB16_S1_S1("bram23");
	  bram24 = new RAMB16_S1_S1("bram24");
	  bram25 = new RAMB16_S1_S1("bram25");
	  bram26 = new RAMB16_S1_S1("bram26");
	  bram27 = new RAMB16_S1_S1("bram27");
	  bram28 = new RAMB16_S1_S1("bram28");
	  bram29 = new RAMB16_S1_S1("bram29");
	  bram30 = new RAMB16_S1_S1("bram30");
	  bram31 = new RAMB16_S1_S1("bram31");

	  conv = new NETMEM_RAM_WRAPPER("conv");
	  conv->addr(addr);
	  conv->din(din);
	  conv->dout(dout);
	  conv->r(r);
	  conv->wb(wb);
	  conv->wh(wh);
	  conv->wl(wl);
	  conv->clk(clk);

	  dbgconv = new NETMEM_RAM_DBGWRAPPER("dbgconv");
	  dbgconv->DO(dbgDO);
	  dbgconv->ADDR(dbgADDR);
	  dbgconv->DI(dbgDI);
	  dbgconv->EN(dbgEN);
	  dbgconv->CLK(dbgCLK);
	  dbgconv->WE(dbgWE);
	  dbgconv->RST(dbgRST);

	  
	  bram00->ADDRA(ADDR); bram00->ENA(EN); bram00->WEA(WE0); bram00->CLKA(CLK); bram00->SSRA(SSR);
	  bram01->ADDRA(ADDR); bram01->ENA(EN); bram01->WEA(WE0); bram01->CLKA(CLK); bram01->SSRA(SSR);
	  bram02->ADDRA(ADDR); bram02->ENA(EN); bram02->WEA(WE0); bram02->CLKA(CLK); bram02->SSRA(SSR);