xram2vcd.py

改进的基于6个mips核的NOC网络

import os, sys, string

VARS = (
    ('clock',1,'aa'),
    ('enable',1,'ab'),
    ('reset',1,'ac'),
    ('clk', 1, 'a'),
    ('ctrl_enable', 1, 'b'),
    ('imem_en', 1, 'c'),
    ('dmem_en', 1, 'd'),
    ('pipe_en', 1, 'e'),
    ('ifidwrite', 1, 'f'),
    ('pcwrite', 1, 'g'),
    ('hazard', 1, 'h'),
    ('reg1addr', 5, 'i'),
    ('reg2addr', 5, 'j'),
    ('sig32', 10, 'x'),
    ('c1b', 1, 'z'),
    )

pcVARS = ( ('pc', 32, 'ba'), )
imemVARS = ( ('imem', 32, 'ca'), )

FILES = []

while '-f' in sys.argv:
    ix = sys.argv.index('-f')
    fn = sys.argv[ix+1]
    sig = sys.argv[ix+2]
    ex = 'siglist = %sVARS'%sig
    exec ex
    FILES.append( (fn, siglist) )

# if len(FILES) == 0 : FILES.append( ('xram.dump', sigVARS) )

f = open('xram.dump','rb')

vcd = open('xram.vcd', 'w')

vcd.write('$scope module xram $end\n')
for v in VARS : vcd.write( '$var wire %d %s %s $end\n'%(v[1], v[2], v[0]) )
vcd.write('$upscope $end\n$enddefinitions $end\n$dumpvars\n')
for v in VARS : vcd.write( 'b%s %s\n'%(v[1]*'0', v[2]) )
vcd.write('$end\n')

t = 1
while 1 :
    b = []
    for x in range(4):
        c = f.read(1)
        if c == '' : break
        b.append( ord(c) & 0xff )
    if len(b) != 4 : break

    w = (b[0]<<24) | (b[1]<<16) | (b[2]<<8) | b[3]

    vcd.write('#%d\n'%t)
    t=t+1
    
    for v in VARS :
        mask = 0x0
        for x in range(v[1]):
            mask = mask << 1;
            mask = mask | 0x1
        value = w & mask
        w = w >> v[1]

        bin = ''
        for x in range(v[1]):
            if value & 0x1 : bin = '1'+bin
            else : bin = '0'+bin
            value = value >> 1

        vcd.write('b%s %s\n'%(bin,v[2]))

vcd.close()