netgen.py

改进的基于6个mips核的NOC网络

import os, sys, string

if len(sys.argv) != 3 :
    print 'Usage: python getnet.py <xdim> <ydim>'
    sys.exit(1)
    
X, Y = map( int, sys.argv[1:3] )
name = 'NETWORK%dx%d'%(X,Y)
lname = string.lower(name)

hf = open(lname+'.h','w')
cf = open(lname+'.cpp','w')

##########################################################################################

hf.write('#include <systemc.h>\n#include "router.h"\n\n')
hf.write('SC_MODULE(NETWORK%dx%d)\n{\n\n'%(X,Y))
hf.write('\tsc_in<bool> clk, rst;\n\n')

# ports of the network
for x in range(X):
    for y in range(Y):
        hf.write('\tsc_in< sc_bv<FLIT_LEN> > x%dy%ddin;\n'%(x,y))
        hf.write('\tsc_out< sc_bv<FLIT_LEN> > x%dy%ddout;\n'%(x,y))
        hf.write('\tsc_in< bool > x%dy%dreq_net;\n'%(x,y))
        hf.write('\tsc_out< bool > x%dy%dack_net;\n'%(x,y))
        hf.write('\tsc_in< bool > x%dy%dack_dp;\n'%(x,y))
        hf.write('\tsc_out< bool > x%dy%dreq_dp;\n'%(x,y))

# routers
hf.write('\n')
for x in range(X):
    for y in range(Y):
        hf.write('\tECUBE_ROUTER *x%dy%d;\n'%(x,y))

# connections between routers
hf.write('\n')
for x in range(X):
    for y in range(Y):
        nn, nx, ny = 'x%dy%d'%(x,y),'x%dy%d'%((x+1)%X,y), 'x%dy%d'%(x,(y+1)%Y)

        for p, n in ( (nn,nx), (nn,ny) ):
            hf.write('\tsc_signal< sc_bv<FLIT_LEN> > %s_%s_data;\n'%(p,n))
            signals = ( 'ch0req', 'ch0ack', 'ch1req', 'ch1ack' ) 
            hf.write('\tsc_signal< bool > %s;\n'%(string.join( map(lambda s,p=p,n=n:'%s_%s_%s'%(p,n,s),signals), ', ')))
        hf.write('\n')

# address signals for routers
for n in range(max(X,Y)):
    hf.write( '\tsc_signal< sc_uint<ADDRESS_LEN> > addr%d;\n'%n)
    
# constructor
hf.write('\n\tSC_CTOR(NETWORK%dx%d){\n'%(X,Y))

# instantiate routers
for x in range(X):
    for y in range(Y):
        hf.write('\t\tx%dy%d = new ECUBE_ROUTER("x%dy%d");\n'%(x,y,x,y))

# address signals for routers
hf.write('\n')
for n in range(max(X,Y)):
    hf.write( '\t\taddr%d = %d;\n'%(n,n))

# connect routers to previous and next in both dimensions
hf.write('\n')
for x in range(X):
    for y in range(Y):
        n, nx, ny, px, py = 'x%dy%d'%(x,y), 'x%dy%d'%((x+1)%X,y), 'x%dy%d'%(x,(y+1)%Y), 'x%dy%d'%((x-1)%X,y), 'x%dy%d'%(x,(y-1)%Y)
        hf.write('\t\t%s->clk(clk); %s->rst(rst);\n'%(n,n))
        hf.write('\t\t%s->xaddr(addr%d); %s->yaddr(addr%d);\n'%(n,x,n,y))
        hf.write('\t\t%s->din(%sdin); %s->dout(%sdout);\n'%(n,n,n,n))
        hf.write('\t\t%s->dreq_in(%sreq_net); %s->dack_out(%sack_net);\n'%(n,n,n,n))
        hf.write('\t\t%s->dreq_out(%sreq_dp); %s->dack_in(%sack_dp);\n'%(n,n,n,n))

        hf.write('\t\t%s->xin(%s_%s_data);\n'%(n,px,n))
        hf.write('\t\t%s->x0req_in(%s_%s_ch0req); %s->x0ack_out(%s_%s_ch0ack);\n'%(n,px,n,n,px,n))
        hf.write('\t\t%s->xout(%s_%s_data);\n'%(n,n,nx))
        hf.write('\t\t%s->x0req_out(%s_%s_ch0req); %s->x0ack_in(%s_%s_ch0ack);\n'%(n,n,nx,n,n,nx))

        hf.write('\t\t%s->yin(%s_%s_data);\n'%(n,py,n))
        hf.write('\t\t%s->y0req_in(%s_%s_ch0req); %s->y0ack_out(%s_%s_ch0ack);\n'%(n,py,n,n,py,n))
        hf.write('\t\t%s->yout(%s_%s_data);\n'%(n,n,ny))
        hf.write('\t\t%s->y0req_out(%s_%s_ch0req); %s->y0ack_in(%s_%s_ch0ack);\n'%(n,n,ny,n,n,ny))

        hf.write('\t\t%s->x1req_in(%s_%s_ch1req); %s->x1ack_out(%s_%s_ch1ack);\n'%(n,px,n,n,px,n))
        hf.write('\t\t%s->x1req_out(%s_%s_ch1req); %s->x1ack_in(%s_%s_ch1ack);\n'%(n,n,nx,n,n,nx))

        hf.write('\t\t%s->y1req_in(%s_%s_ch1req); %s->y1ack_out(%s_%s_ch1ack);\n'%(n,py,n,n,py,n))
        hf.write('\t\t%s->y1req_out(%s_%s_ch1req); %s->y1ack_in(%s_%s_ch1ack);\n'%(n,n,ny,n,n,ny))
        hf.write('\n')
        
hf.write('\t}\n};\n\n')

##########################################################################################
# network testbench


if 0 : 
    ##### network variable

    cf.write('\t%s %s("%s");\n\n'%(name,lname,lname))

    # create data processors
    for x in range(X):
        for y in range(Y):
            c = 'x%dy%d'%(x,y)
            d = 'dp_'+c
            drv = 'drv%d%d'%(x,y)
            cf.write('\tNETmMIPS %s("%s");\n'%(d,d))

    # signal connected to ports of network
    for x in range(X):
        for y in range(Y):
            cf.write('\tsc_signal< sc_bv<FLIT_LEN> > x%dy%ddin;\n'%(x,y))
            cf.write('\tsc_signal< sc_bv<FLIT_LEN> > x%dy%ddout;\n'%(x,y))
            cf.write('\tsc_signal< bool > x%dy%dreq_net;\n'%(x,y))
            cf.write('\tsc_signal< bool > x%dy%dack_net;\n'%(x,y))
            cf.write('\tsc_signal< bool > x%dy%dack_dp;\n'%(x,y))
            cf.write('\tsc_signal< bool > x%dy%dreq_dp;\n\n'%(x,y))


    # connect signals to net
    cf.write('\t%s.clk(clk); %s.rst(rst);\n'%(lname,lname))
    for x in range(X):
        for y in range(Y):
            c = 'x%dy%d'%(x,y)
            for s in ( 'din', 'dout', 'req_net', 'ack_net', 'ack_dp', 'req_dp' ):
                cf.write('\t%s.%s%s(%s%s);\n'%(lname,c,s,c,s))


    ### create signals specific to data processors
    ##for x in range(X):
    ##    for y in range(Y):
    ##        c = 'x%dy%d'%(x,y)
    ##        d = 'dp_'+c
    ##        drv = 'drv%d%d'%(x,y)

    ##        for s in ('reg_data_in','reg_data_out'):
    ##            cf.write('\tsc_signal< sc_bv<32> > %s_%s;\n'%(d,s))

    ##        for s in ('write_data','write_addr','send','read','data_rdy','send_rdy'):
    ##            cf.write('\tsc_signal< bool > %s_%s;\n'%(d,s))
    ##        cf.write('\tsc_signal<bool> %s_en;\n'%drv)

    ##        cf.write('\n')

    ### connect signals specific to data processors
    ##for x in range(X):
    ##    for y in range(Y):
    ##        c = 'x%dy%d'%(x,y)
    ##        d = 'dp_'+c
    ##        drv = 'drv%d%d'%(x,y)

    ##        cf.write('\t%s.clk(clk); %s.rst(rst);\n'%(d,d))
    ##        cf.write('\t%s.clk(clk); %s.rst(rst); %s.en(%s_en);\n'%(drv,drv,drv,drv))
    ##        cf.write('\t%s.x = %d; %s.y = %d; %s.maxx = %d; %s.maxy = %d;\n'%(drv,x,drv,y,drv,X-1,drv,Y-1))

    ##        for s in ('reg_data_in','write_data','write_addr','send','read','reg_data_out','data_rdy','send_rdy'):
    ##            cf.write('\t%s.%s(%s_%s);\n'%(d,s,d,s))
    ##            cf.write('\t%s.%s(%s_%s);\n'%(drv,s,d,s))
    ##        cf.write('\n')

    # connect signals specific to data processors
    for x in range(X):
        for y in range(Y):
            c = 'x%dy%d'%(x,y)
            d = 'dp_'+c
            drv = 'drv%d%d'%(x,y)

            cf.write('\t%s.clock(clk); %s.reset(rst); %s.enable(en);\n'%(d,d,d))

    # connect network signals to data processors
    for x in range(X):
        for y in range(Y):
            c = 'x%dy%d'%(x,y)
            d = 'dp_'+c
            cf.write('\t%s.data_in(%sdout);\n'%(d,c))
            cf.write('\t%s.data_out(%sdin);\n'%(d,c))
            cf.write('\t%s.req_out(%sreq_net);\n'%(d,c))
            cf.write('\t%s.ack_in(%sack_net);\n'%(d,c))
            cf.write('\t%s.ack_out(%sack_dp);\n'%(d,c))
            cf.write('\t%s.req_in(%sreq_dp);\n'%(d,c))
            cf.write('\n')

    # memory debug signals
    for x in range(X):
        for y in range(Y):
            c = 'x%dy%d'%(x,y)
            d = 'dp_'+c
            for m in ( 'ram', 'rom' ):
                cf.write( '\tsc_signal<sc_uint<32> > %s_%sADDR;\n'%(d,m) )
                cf.write( '\tsc_signal<sc_int<32> > %s_%sDI;\n'%(d,m) )
                cf.write( '\tsc_signal<sc_int<32> > %s_%sDO;\n'%(d,m) )
                for s in ( 'EN', 'CLK', 'WE', 'RST' ):
                    cf.write( '\tsc_signal<bool> %s_%s%s;\n'%(d,m,s) )

            cf.write('#ifdef USEXRAM\n') 
            cf.write( '\tsc_signal< sc_int<32> > %s_xDO;\n'%d )
            cf.write( '\tsc_signal< sc_uint<32> > %s_xADDR;\n'%d )
            cf.write( '\tsc_signal< bool > %s_xCLK, %s_xWE;\n'%(d,d) )
            cf.write('#endif\n')
            cf.write('\n')
            
    for x in range(X):
        for y in range(Y):
            c = 'x%dy%d'%(x,y)
            d = 'dp_'+c
            for m in ( 'ram', 'rom' ):
                for s in ( 'ADDR', 'DI', 'DO', 'EN', 'CLK', 'WE', 'RST' ):
                    cf.write( '\t%s.%s%s(%s_%s%s);\n'%(d,m,s,d,m,s) )

            cf.write('#ifdef USEXRAM\n')
            for s in ( 'ADDR', 'DO', 'CLK', 'WE' ):
                cf.write( '\t%s.x%s(%s_x%s);\n'%(d,s,d,s) )
            cf.write('#endif\n')
            cf.write('\n')

            
    for x in range(X):
        for y in range(Y):
            c = 'x%dy%d'%(x,y)
            d = 'dp_'+c
            cf.write('\tsc_signal< sc_bv<32> > %s_pc;\n'%d)
            cf.write('\t%s.bus_pc(%s_pc);\n'%(d,d))

##########################################################################################
# tracing

cf.write('#ifndef NOVCD\n');

# network ports
for x in range(X):
    for y in range(Y):
        c = 'x%dy%d'%(x,y)
        for s in ('din','dout','req_net','ack_net','req_dp','ack_dp'):
            cf.write('\tsc_trace(tf, benif.%s%s, "dp_%s.net.%s%s");\n'%(c,s,c,c,s))
        cf.write('\n')

# internal connections within network
for x in range(X):
    for y in range(Y):
        nn, nx, ny = 'x%dy%d'%(x,y),'x%dy%d'%((x+1)%X,y), 'x%dy%d'%(x,(y+1)%Y)

        for p, n in ( (nn,nx), (nn,ny) ):
            for s in ( 'data', 'ch0req', 'ch0ack', 'ch1req', 'ch1ack' ):
                cf.write('\tsc_trace(tf, benif.%s->%s_%s_%s, "%s.%s_%s.%s_%s_%s");\n'%(lname,p,n,s,lname,p,n,p,n,s))

# tracing of routers
cf.write('\n')
for x in range(X):
    for y in range(Y):
        nn = 'x%dy%d'%(x,y)
        cf.write('\ttrace_router(tf, benif.%s->%s, "%s.%s.");\n'%(lname,nn,lname,nn))
                
# tracing data processors

for x in range(X):
    for y in range(Y):
        c = 'x%dy%d'%(x,y)
        d = 'dp_'+c
        
        # connection network i/f <-> mips
        cf.write( '\ttrace_netmips(tf, benif.%s, "%s.mips_if.");\n'%(d,d))

        # trace network interface
        cf.write( '\ttrace_netif(tf, benif.%s->netif, "%s.netif.");\n'%(d,d))

        # trace mmips
        cf.write( '#ifdef CACHE\n')
        cf.write( '\ttrace_mips(tf, benif.%s->mips->mips, "%s.mips.");\n'%(d,d))
        cf.write( '#else\n')
        cf.write( '\ttrace_mips(tf, benif.%s->mips, "%s.mips.");\n'%(d,d))
        cf.write( '#endif\n')


cf.write('#endif\n');

# load mips memories
cf.write( '#ifndef CACHE\n' )
for x in range(X):
    for y in range(Y):
        c = 'x%dy%d'%(x,y)
        d = 'dp_'+c
        cf.write( '\tbenif.%s->mips->imem->mem_init("mips_rom.%s.bin");\n'%(d,c))
        cf.write( '\tbenif.%s->mips->imem->mem_dump("mips_rom.%s.0.dump");\n'%(d,c))
        cf.write( '\tbenif.%s->mips->dmem->mem_init("mips_ram.%s.bin");\n'%(d,c))
        cf.write( '\tbenif.%s->mips->dmem->mem_dump("mips_ram.%s.0.dump");\n'%(d,c))
        
cf.write( '#else\n' )
for x in range(X):
    for y in range(Y):
        c = 'x%dy%d'%(x,y)
        d = 'dp_'+c
        cf.write( '\tbenif.%s->mips->memory->memory->mem_init("mem.%s.bin");\n'%(d,c))
        cf.write( '\tbenif.%s->mips->memory->memory->mem_dump("mem.%s.0.dump");\n'%(d,c))
cf.write( '#endif\n\n')


# dump mips memories
sys.stdout.write( '#ifndef CACHE\n' )
for x in range(X):
    for y in range(Y):
        c = 'x%dy%d'%(x,y)
        d = 'dp_'+c
        sys.stdout.write( '\tbenif.%s->mips->dmem->mem_dump("mips_ram.%s.dump");\n'%(d,c))
        
sys.stdout.write( '#else\n' )
for x in range(X):
    for y in range(Y):
        c = 'x%dy%d'%(x,y)
        d = 'dp_'+c
        sys.stdout.write( '\tbenif.%s->mips->memory->memory->mem_dump("mem.%s.dump");\n'%(d,c))
sys.stdout.write( '#endif\n\n')

hf.close()
cf.close()