cache_memory.h

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   cache_memory.h
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   Behavioral model of cache memory
 *
 *
 */

#ifndef CACHEMEM_H_INCLUDED
#define CACHEMEM_H_INCLUDED

#include <systemc.h>

SC_MODULE(CACHE_MEMORY)
{
  sc_bv<TAG_BITS> tags[CACHE_BLOCKS];
  bool valid_bits[CACHE_BLOCKS];
  sc_bv<32> memW0[CACHE_BLOCKS], memW1[CACHE_BLOCKS], memW2[CACHE_BLOCKS], memW3[CACHE_BLOCKS];
	
  sc_in<bool> clk;
  sc_in< sc_bv<32> > din;
  sc_in< bool > valid_in;
  sc_in< sc_bv<TAG_BITS> > tagi;
  sc_in< sc_bv<INDEX_BITS> > index;
  sc_in< sc_bv<OFFSET_BITS> > offset;
  sc_in< bool > we;
  sc_in< bool > en;  
  
  sc_out< sc_bv<32> > dout;
  sc_out< sc_bv<TAG_BITS> > tago;
  sc_out< bool > valid;

  
  SC_CTOR(CACHE_MEMORY)
	{
	  SC_CTHREAD(memory_process,clk.pos());
	}

  void memory_process(){
	sc_bv<32> out, di;
	sc_bv<TAG_BITS> to;
	bool v;	
	sc_uint<OFFSET_BITS> off;
	sc_uint<INDEX_BITS> ix;

	while(true){
	
	  out = dout.read();
	  di = din.read();
	  to = tago.read();
	  v = valid.read();
	  off = offset.read();
	  ix = index.read();
	  
	  if( en.read() ){
		// !!!!!!!!! read-before-write !!!!!!!!!!!
		switch( off ){
		case 0 : out = memW0[ix]; break;
		case 1 : out = memW1[ix]; break;
		case 2 : out = memW2[ix]; break;
		case 3 : out = memW3[ix]; break;
		}
		to = tags[ix];
		v = valid_bits[ix];	

		if( we.read() ){
		  switch( off ){
		  case 0 : memW0[ix] = di; break;
		  case 1 : memW1[ix] = di; break;
		  case 2 : memW2[ix] = di; break;
		  case 3 : memW3[ix] = di; break;
		  }
		  tags[ix] = tagi.read();
		  valid_bits[ix] = valid_in.read();
		}
	  }
	  
	  dout.write(out);
	  tago.write(to);
	  valid.write(v);

	  wait();
	}
  }
    
};

#endif