cache_mainmem.h

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   cache_mainmem.h
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   
 *
 *
 */


#ifndef CACHE_MAINMEM_H_INCLUDED
#define CACHE_MAINMEM_H_INCLUDED

#include <systemc.h>
#include "mips.h"
#include "mem32k.h"

#define MEM_PARTITION_BITS 14
#define MEM_OFFSET_0 0x0
#define MEM_OFFSET_1 0x4000


SC_MODULE(CACHE_MAINMEM_ARBITER)
{
  sc_in< bool > clk;

  sc_in< sc_bv<32> > addr0, addr1; 
  sc_in< sc_bv<32> > din0, din1;
  sc_out< sc_bv<32> > dout;
  sc_in< bool > ww0, ww1; 
  sc_in< bool > wb0, wb1; 
  sc_in< bool > r0, r1; 
  sc_out< bool > rdy0, rdy1;
  
  sc_out < sc_uint<32> > mem_addr;
  sc_in< sc_int<32> > mem_dout;
  sc_out< sc_int<32> > mem_din;
  sc_out< bool > mem_wb, mem_ww;
  sc_out< bool > mem_r;
  sc_out< bool > mem_clk;	

  sc_signal< sc_bv<32> > addr0_reg, addr1_reg; 
  sc_signal< sc_bv<32> > din0_reg, din1_reg;
  sc_signal< bool > ww0_reg, ww1_reg; 
  sc_signal< bool > wb0_reg, wb1_reg; 
  sc_signal< bool > r0_reg, r1_reg; 

  sc_signal< sc_bv<2> > grant, n_grant;
  sc_signal< bool > reg0, reg1, clr0, clr1;
  
  void select();
  void output();
  void reg();
  
  SC_CTOR(CACHE_MAINMEM_ARBITER)
	{	  
	  SC_METHOD(select);
	  sensitive << grant << clk
				<< addr0 << addr1 << din0 << din1 
				<< ww0 << ww1 << wb0 << wb1	<< r0 << r1 
				<< addr0_reg << addr1_reg << din0_reg << din1_reg 
				<< ww0_reg << ww1_reg << wb0_reg << wb1_reg	<< r0_reg << r1_reg ;

	  SC_METHOD(output);
	  sensitive << mem_dout;
	  
	  SC_METHOD(reg);
	  sensitive_pos << clk;
	}
    
};

SC_MODULE(CACHE_MAINMEM)
{
  sc_in< bool > clk;
  sc_in< sc_bv<32> > addr0, addr1; 
  sc_in< sc_bv<32> > din0, din1;
  sc_out< sc_bv<32> > dout;
  sc_in< bool > ww0, ww1; 
  sc_in< bool > wb0, wb1; 
  sc_in< bool > r0, r1; 
  sc_out< bool > rdy0, rdy1;

  CACHE_MAINMEM_ARBITER *arbiter;
  MEM32K *memory;
  
  sc_signal< sc_uint<32> > mem_addr;
  sc_signal< sc_int<32> > mem_dout;
  sc_signal< sc_int<32> > mem_din;
  sc_signal< bool > mem_ww, mem_wb;
  sc_signal< bool > mem_r;
  sc_signal< bool > mem_clk;	

  // download/upload
  sc_out<sc_int<32> > ramDO;
  sc_in<sc_uint<32> > ramADDR;
  sc_in<sc_int<32> > ramDI;
  sc_in<bool> ramEN;
  sc_in<bool> ramCLK;
  sc_in<bool> ramWE;
  sc_in<bool> ramRST;

  SC_CTOR(CACHE_MAINMEM)
	{
	  arbiter = new CACHE_MAINMEM_ARBITER("arbiter");
	  memory = new MEM32K("memory");
	  
	  arbiter->clk(clk);
	  arbiter->addr0(addr0); arbiter->addr1(addr1); 
	  arbiter->din0(din0); arbiter->din1(din1);
	  arbiter->dout(dout);
	  arbiter->ww0(ww0); arbiter->ww1(ww1); 
	  arbiter->wb0(wb0); arbiter->wb1(wb1); 
	  arbiter->r0(r0); arbiter->r1(r1); 
	  arbiter->rdy0(rdy0); arbiter->rdy1(rdy1);
	  
	  arbiter->mem_addr(mem_addr); memory->addr(mem_addr);
	  arbiter->mem_dout(mem_dout); memory->dout(mem_dout);
	  arbiter->mem_din(mem_din); memory->din(mem_din);
	  arbiter->mem_ww(mem_ww); memory->ww(mem_ww);
	  arbiter->mem_wb(mem_wb); memory->wb(mem_wb);
	  arbiter->mem_r(mem_r); memory->r(mem_r);
	  arbiter->mem_clk(mem_clk); memory->clk(mem_clk);
	  
	  memory->dbgDO(ramDO);
	  memory->dbgADDR(ramADDR);
	  memory->dbgDI(ramDI);
	  memory->dbgEN(ramEN);
	  memory->dbgCLK(ramCLK);
	  memory->dbgWE(ramWE);
	  memory->dbgRST(ramRST);
	}
  
};

#endif